AES256GCM 10G25G IP Core Datasheet
Core Facts |
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Provided with Core |
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Documentation |
User Guide, Design Guide |
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Design File Formats |
Encrypted File |
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Instantiation Templates |
VHDL |
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Reference Designs & Application Notes |
Quartus Project, See Reference Design Manual |
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Additional Items |
Demo on A10SoC, Agilex F-Series development kit |
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Support |
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Support Provided by Design Gateway Co., Ltd. |
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Design Gateway Co.,Ltd
E-mail: ip-sales@design-gateway.com
URL: design-gateway.com
Features
· Support AES-GCM mode standard.
· Support 256-bit key size, 96-bit iv size.
· Support zero-length AAD or data input.
· Peak throughput rate at 128 Mbits/MHz.
· Speed up to 30.72 Gbps @240MHz.
Table 1: Example Implementation Statistics
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Family |
Example Device |
Fmax (MHz) |
ALMs |
Registers1 |
Design Tools |
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Agilex F-Series |
AGFB014R24A2E2VR0 |
240 |
16588.8 |
10695 |
Quartus 20.4 |
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Arria10 SX |
10AS066N3F40E2SGE2 |
185.71 |
15691.8 |
5339 |
Quartus 20.4 |
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Stratix10 GX2 |
1SG280HU2F50E1VG |
180 |
15748.1 |
8162 |
Quartus 20.4 |
Notes:
1) Actual logic resource is dependent on percentage of unrelated logic.
2) The results were obtained from implementation in the same environment, but have not been tested on the actual board.
Figure 1: Block Diagram
General Description
AES256-GCM-10G25G IP Core (AES256GCM10G25GIP) implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application, including IPSEC, MACSEC and TLS (Transport Layer Security) versions 1.2 and 1.3. Additionally, AES-GCM is used in fiber channel communications and storage applications.
AES256GCM10G25GIP works with 256-bit AES-key and 96-bit Initialization Vector (IV). It can provide confidentiality and data authentication by using Additional Authenticated Data (AAD) and authentication tag. It is designed to support zero-length plaintext/ciphertext input which is the special case of GCM mode, called GMAC, and also support zero-length AAD.
There are 2 main operations in AES-GCM, AES encryption/decryption by GCTR and tag calculation by GHASH algorithm. AES256GCM10G25GIP can operate 128-bit data every clock cycle, as a result, it can operate at speed up to 30.72 Gbps at 240MHz, which can be used effectively on 10G/25G Ethernet.
Functional Description
AES256GCM10G25G interface signals can be divided into 3 parts, i.e., Key setting signals, parameter setting signals and data control signals.
Table 2: Interface signals of AES256GCM10G25GIP
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Signal name |
Dir |
Description |
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RstB |
In |
IP core system reset. Active low. |
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Clk |
In |
IP core system clock. |
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version[31:0] |
Out |
32-bit version number of AES256GCM10G25GIP. |
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Key setting signals |
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KeyInValid |
In |
KeyInValid is a user signal to specify data valid of KeyIn. Assert to ‘1’ to set up KeyIn into AES256GCM10G25GIP. |
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KeyInBusy |
Out |
KeyInBusy specifies busy status of Key setting. Assert to ‘1’ after user set KeyInValid, until the last cycle of operation. KeyInValid or Start will be ignored while KeyInBusy is ‘1’.
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KeyInFinish |
Out |
KeyInFinish specifies finish status of Key setting. Assert to ‘1’ at the last cycle of operation.
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KeyIn[255:0] |
In |
KeyIn is 256-bit key data for AES block cipher in CTR mode of operation. KeyIn must be valid when KeyInValid is asserted to ‘1’.
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Parameter setting signals |
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Start |
In |
Start is a user signal to start AES256GCM10G25GIP operation. |
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DecryptionEn |
In |
DecryptionEn is a user signal to specify mode of operation. DecryptionEn=‘0’ for encryption, DecryptionEn=‘1’ for decryption. DecryptionEn must be valid during operation. |
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Bypass |
In |
Bypass is a user signal to specify bypass mode of operation. Bypass=‘0’ for encryption/decryption mode, Bypass=‘1’ for bypass mode. Bypass must be valid during operation.
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Busy |
Out |
Busy specifies busy status of operation. Busy is active after user set Start, until operation is done. KeyInValid or Start will be ignored while Busy is ‘1’.
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Finish |
Out |
Finish specifies finish status of AES256GCM10G25GIP. Assert to ‘1’ at the last cycle of operation.
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IvIn[95:0] |
In |
IvIn is 96-bit IV data for AES block cipher in CTR mode of operation. IvIn must be valid during operation. |
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AadInCount[15:0] |
In |
AadInCount is the number of AAD in byte. AadInCount must be valid during operation. |
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DataInCount[15:0] |
In |
DataInCount is the number of input data in byte. DataInCount must be valid during operation. |
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Data control signals |
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DataInRd |
Out |
DataInRd is a control signal to read DataIn. |
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DataIn[127:0] |
In |
DataIn is 128-bit input data, both of AAD and data. DataIn must be valid when DataInRd is asserted to ‘1’. |
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DataOutValid |
Out |
DataOutValid specifies data valid for DataOut. Assert to ‘1’ when cipher data is valid for encryption mode or plain data is valid for decryption mode. |
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DataOut[127:0] |
Out |
DataOut is 128-bit data output of AES256GCM10G25GIP. Valid when DataOutValid is asserted to ‘1’. |
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TagOutValid |
Out |
TagOutValid specifies tag valid. Assert to ‘1’ when tag calculation is done. |
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TagOut[127:0] |
Out |
TagOut is 128-bit tag output of AES256GCM10G25GIP. Valid when TagOutValid is asserted to ‘1’. |
Figure 2: AES256GCM10G25G timing diagram in encryption mode
AES256GCM10G25G operation is as simple as 3 steps to use as below.
1. Key setting
Key setting is the first step to use AES256GCM10G25G. As shown in Figure 2, AES256GCM10G25G is started key setting process when KeyInValid=‘1’. KeyInBusy is set to be ‘1’ in the next cycle. KeyInFinish is active only one clock at the last cycle of process and KeyInBusy is cleared to ‘0’ in the next cycle. After that, this KeyIn is used for every process and can be changed via KeyInValid is asserted to ‘1’.
2. Parameter setting
After key setting, AES256GCM10G25G starts the process when Start is asserted to ‘1’. DecryptionEn, Bypass, KeyIn, IvIn, AadInCount and DataInCount must be valid when Start=‘1’ and be hold during operation. User can set DecryptionEn to ‘0’ and Bypass to ‘0’ for operating in encryption mode as shown in Figure 2 or set DecryptionEn to ‘1’ and Bypass to ‘0’ for operating in decryption mode as shown in Figure 3. And set Bypass to ‘1’ for operating in Bypass mode as shown in Figure 4.
Figure 3: AES256GCM10G25G timing diagram in decryption mode
Figure 4: AES256GCM10G25G timing diagram in Bypass mode
For the best performance of process, Figure 5 shows the timing diagram of continuous and pipelining process. User can use Finish signal as a trigger signal for setting new parameters and sending new start command in next cycle.
Figure 5: Continuous and pipelining operation
3. Data control
According to DataIn width is 128 bits (16 bytes) and AES256GCM10G25G is designed to read DataIn every clock cycle when AES256GCM10G25G is ready to start encryption/decryption process. After Start is set to begin the operation, user must prepare first valid DataIn[127:0]. Then user can use DataInRd signal as a trigger signal for setting the next DataIn continuously. If AadInCount is not aligned to 128 bits (16 bytes), the last 128-bit AAD must be right-padded with zeros.
Figure 6: DataIn arrangement for 30-byte AAD and 15-byte data
Figure 6 is a detailed example of 30-byte AAD and 15-byte data preparation. DataIn0, DataIn1 and DataIn2 is represent as DataIn[127:0] in the first, second and third clock cycle respectively. The first 16-byte of AAD (AADBytes0-AADBytes15) is set as DataIn0[127:120], ..., DataIn0[7:0]. The remained 14-byte of AAD (AADBytes16-AADBytes29) is set as DataIn1[127:120], ..., DataIn1[23:16] and DataIn1[15:0] must be zeros. Then the remained 15-byte data (DATABytes0-DATABytes14) must be set as DataIn2[127:8].
As shown in Figure 2 and Figure 3, at last operation cycle, the Finish signal is asserted to ‘1’ and Busy signal is cleared to ‘0’ in the next cycle. TagOutValid is active only one clock on the next clock after Busy is cleared to ‘0’. In case of Bypass mode is active as shown in Figure 4, the TagOut is not calculated and TagOutValid is not active.
Verification Methods
AES256-GCM-10G25G IP Core functionality were verified on real board design by using Agilex F-Series development kit and Arria10 SoC development board.
Recommended Design Experience
The user must be familiar with HDL design methodology to integrate this IP into system.
Ordering Information
This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. For pricing and additional information about this product using the contact information on the front page of this datasheet.
Revision History
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Revision |
Date |
Description |
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1.00 |
1/Oct/2022 |
New release |
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1.02 |
26/Oct/2022 |
New design to improve performance |
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1.03 |
23/Feb/2023 |
- Add Bypass Feature. - Improve performance. - Add more resource information. |