UDP100G-IP Demo Instruction
Rev1.1 12-Jul-23
3 Test result when using FPGA and TestPC
4 Test result when using two FPGAs
4.3 Send and Receive Data Test (Half duplex test)
1 Overview
This document shows the example to run UDP100G-IP demo by using two test environments. First is run by using one FPGA board transferring UDP payload data with TestPC which runs test application for transferring the data via 100Gb Ethernet. Test performance and data lost rate on the first environment depend on the TestPC resource. Second is run by using two FPGA boards for transferring 100Gb Ethernet data together. The second environment achieves the best performance for transferring UDP payload data via 100Gb Ethernet by using UDP100G-IP.
In the document, topic 2 shows the example to set up 100Gb Ethernet card on TestPC to get the good performance for transferring data via 100Gb Ethernet when running the test by using the first test environment, FPGA and Test PC. Topic 3 shows the example console and test result when running under the first test environment. Finally, topic 4 shows the example console when running the second test environment, FPGA and FPGA. More details of each topic are described as follows.
2 PC Setup
Before running demo, please check the network setting on PC. The example for setting 100Gb Ethernet card is described as follows.
2.1 IP Setting
Figure 2‑1 Set IP address
1) Open Local Area Connection Properties of 100-Gb connection, as shown in the left window of Figure 2‑1.
2) Select “TCP/IPv4” and then click Properties.
3) Set IP address = 192.168.100.25 and Subnet mask = 255.255.255.0, as shown in the right window of Figure 2‑1.
2.2 Ethernet Adapter Setting
Figure 2‑2 Set frame size = jumbo frame
1) On Local Area Connection Properties window, click “Configure” as shown in Figure 2‑2.
2) On Advanced Tab, select “Jumbo Packet”. Set Value to “9014 Bytes” for Jumbo Frame support or set value to “1514 Bytes” for non-Jumbo Frame support.
Figure 2‑3 Set interrupt moderation
3) Select “Interrupt Moderation” and set value to “Disabled”, as shown in Figure 2‑3.
Figure 2‑4 Set Number of RSS Queues and RSS Base Processor Number
4) Set Maximum Number of RSS Queues to be greater than 4. For example, set to 8 Queues.
5) When Ethernet card has more than one Ethernet port, RSS Base Processor Number of each Ethernet port must not be overlapped. For example, there are two Ethernet ports and all ports set Max num of RSS queues to 8. The RSS base processor number of each Ethernet port is set to 0 and 8 respectively.
6) Click “OK” button to save and exit all setting windows.
2.3 Power Option Setting
Figure 2‑5 Power options
1) Open Control Panel and select Power Options, as shown in the left window of Figure 2‑5.
2) Set High Performance plan, as shown in the right window of Figure 2‑5.
2.4 Firewall Setting
Figure 2‑6 Firewall setting
1) Open Control Panel and select Windows Firewall.
2) Click “Turn Windows Firewall on or off”.
3) Select Turn off Firewall under Private and Public network settings.
4) Click OK button to confirm the setting.
3 Test result when using FPGA and TestPC
3.1 Display UDPIP parameters
Select ‘0’ to check current parameter in the demo. There are seven parameters in Client mode or eight parameters in Fixed MAC mode displayed on the console.
Figure 3‑1 Display current parameter result
1) Mode : Set initialization mode of UDP100G-IP to be Client or Fixed MAC. To run with PC, it is recommended to initialize the IP in client mode.
2) FPGA MAC address : 48-bit hex value to be MAC address of FPGA. Default value is 0x000102030405.
3) FPGA IP : IP address of FPGA. Default value is 192.168.100.42.
Note: This value is used to be FPGA IP address, parameter for test application on PC.
4) FPGA port number : Port number of FPGA. Default value is 4000.
Note: This value is used to be FPGA port, parameter for test application on PC.
5) Target MAC address (displayed when running Fixed MAC mode only) : 48-bit hex value to be MAC address of the target device. Default value is 0x554433221100.
6) Target IP : IP address of the target device (100 Gb Ethernet on PC). Default value is 192.168.100.25.
7) Target port number (Target->FPGA) : Port number of the target device to send UDP payload data to FPGA. Default value is 61000.
Note: This value is used to be PC port, parameter for test application on PC in transmit mode.
8) Target port number (FPGA->Target) : Port number of the target device to receive UDP payload data from FPGA. Default value is 60000.
Note: This value is used to be PC port, parameter for test application on PC in receive mode.
To change some parameters, user can set by using menu [1] (Reset UDPIP parameters).
3.2 Reset UDPIP parameters
Select ‘1’ to change IP parameters or send reset to UDP100G-IP. After user selects this menu, the current parameters are displayed on the console. User enters ‘x’ to use the same parameters while other keys are entered to change some parameters.
There are seven or eight parameters to set in this menu. The parameter is updated to UDP100G-IP when the input is valid. Otherwise, the parameter does not change. After user inputs all parameters, the IP is reset. The description of each parameter is described in topic 3.1 (Display UDPIP parameters). The valid range of each parameter is described as follows.
1) Mode : Input ‘0’ to initialize the IP as client mode.
2) FPGA MAC address : Input 12 digits of hex value. Add “0x” as a prefix to input as hex value.
3) FPGA IP address : A set of four decimal digits is separated by “.”. The valid range of each decimal digit is 0-255.
4) FPGA port number : Valid range is 0-65535.
5) Target MAC address (displayed when running Fixed MAC mode only) : Input 12 digits of hex value. Add “0x” as a prefix to input as hex value.
6) Target IP address : A set of four decimal digits, similar to FPGA IP address. This value is IP address of Test PC.
7) Target port number (Target->FPGA) : Valid range is 0-65535.
8) Target port number (FPGA->Target) : Valid range is 0-65535.
After finishing parameter assignment, new parameter set is displayed on the console. Next, the reset is asserted and the IP starts initialization by using new parameter set. Finally, “IP initialization complete” is shown after IP completes initialization process, as shown in Figure 3‑2.
Figure 3‑2 Change IP parameter in Client mode/Fixed MAC mode
3.3 Send Data Test
To transfer data from FPGA to PC, select ‘2’ to run send data test on FPGA and prepare “udpdatatest.exe” on PC to receive data. User inputs test parameters for sending data on FPGA console. On PC, user inputs test parameters of “udpdatatest” to receive data via Command prompt. The step to run the test is shown as follows.
1) On FPGA console, input two parameters under send data test menu.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
ii) Input packet size: Unit of packet size is byte. Valid value is 64 – 8960. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
Note: If packet size is more than 1472, the packet output from UDP100G-IP is jumbo frame. In this case, Test PC must support jumbo frame.
2) If all inputs are valid, the recommended parameters to run test application on PC are displayed. After that, “Press any key to start data sending ...” is displayed to begin sending data when user enters any key(s).
3) On Command prompt, input test parameters following the recommended value. There are five parameters and two optional parameters for calling “udpdatatest” to receive data.
>> udpdatatest [Dir] [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <Pattern> <Timeout>
i) Dir : Set ‘r’ to receive test data from FPGA
ii) FPGA IP : Set the same value as FPGA IP address
iii) FPGA port : Set the same value as FPGA port number
iv) PC port : Set the same value as target port number (FPGA->Target)
v) ByteLen : Set the same value as “Input transfer size” of step 1)
Optional parameters
vi) Pattern : ‘1’- enable data verification, ‘0’-disable data verification.
Default value is ‘1’ which is applied when there is no input.
vii) Timeout : Timeout in msec unit. Valid value is 50-65536.
It is recommended to set 100 for 100Gb speed.
Default value is 100 which is applied when there is no input.
4) After running the test application, the summary of setting parameter is displayed. Next, the application waits for received data from FPGA.
5) On FPGA console, user enters any key(s) to start sending data. During transferring data, current number of transfer data size is displayed on FPGA console (transmit data size) and Command prompt (receive data size) every second.
6) “Send data complete” is displayed on FPGA console after all data are sent. On PC, test application is finished by two conditions. First, total number of received data is equal to set value (no lost data). Second, the new data is not received until timeout is found. If timeout is found, timeout and error message are displayed on Command prompt. If the test application enables data verification, the first error position is also displayed. Finally, total number of received data and the performance are displayed on FPGA console (transmit performance) and Command prompt (receive performance).
Figure 3‑3 shows the example of send data test when using jumbo frame size with large transfer size. The left window is FPGA console while the right window is Command prompt on PC. When running by large transfer size, it has more chance that PC detects data lost. CPU (PC) is not always available for handling UDP payload data. Therefore, the data may be lost when CPU (PC) handles other tasks.
Figure 3‑3 shows the result when test application runs without data verification. While Figure 3‑4 shows the result when test application runs with data verification. More data is received and the performance is better when test application is run without data verification.
When running the test application with data verification, PC can receive about 23% of all data (31.5 Gbytes of 137 Gbytes). The transmit performance on FPGA is 12408 Mbyte/s while the receive performance on the test application is 2848 Mbyte/s.
Figure 3‑3 Send data test by using jumbo frame when data is lost and verification is disabled
Figure 3‑4 Send data test by using jumbo frame when data is lost and verification is enabled
When using small data size, it has more chance that all data are received correctly. However, using small size, there is much overhead time for transferring a data. The performance result when running small size is not good. As shown in Figure 3‑5, there is no error message on PC when no lost data is found. Performance on PC is less than FPGA console because of the timer accuracy and the overhead time in test application.
Figure 3‑5 Send data test without lost data
If the input is invalid, “Out-of-range input” is displayed. After that, the operation is cancelled, as shown in Figure 3‑6 and Figure 3‑7.
Figure 3‑6 Error from invalid transfer size
Figure 3‑7 Error from invalid packet size
3.4 Receive Data Test
To transfer data from PC to FPGA, select ‘3’ to run receive data test on FPGA and run “udpdatatest.exe” on PC to send data. User inputs test parameters on FPGA for receiving data on FPGA console. On PC, user inputs test parameters of “udpdatatest” to send data on Command prompt. The step to run the test is described as below.
1) On FPGA console, input two parameters in receive data test.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 – 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
ii) Input data verification mode: Set ‘0’ to disable data verification or ‘1’ to enable data verification sent from PC.
2) If inputs are valid, the recommended parameters to run test application on PC are displayed. After that, “Wait data from Target ...” is displayed on the console to wait until some data is received from PC.
3) On Command prompt, input test parameters following the recommended value. There are five parameters for “udpdatatest” and one optional parameter for calling “udpdatatest” to send data.
>> udpdatatest [Dir] [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <pattern>
i) Dir : Set ‘t’ to send test data from PC
ii) FPGA IP : Set the same value as FPGA IP address
iii) FPGA port : Set the same value as FPGA port number
iv) PC port : Set the same value as target port number (Target->FPGA)
v) ByteLen : Set the same value as “Input transfer size” of step 1)
Optional parameters
vi) Pattern : ‘1’- Incremental pattern, ‘0’- dummy pattern.
Default value is ‘1’ which is applied when there is no input.
4) After running the test application, test application starts sending data to FPGA. During transferring data between FPGA and PC, current number of transfer data size is displayed on FPGA console (receive data size) and Command prompt (transmit data size) every second.
5) “Receive data completed” is displayed on FPGA console after FPGA receives all data. Otherwise, timeout is found in FPGA if there is no new data is received for long time. Finally, total number of transfer data size and transfer performance are displayed on FPGA console (receive direction) and Command prompt (transmit direction).
Figure 3‑8 shows the example of receive data test when data verification mode on FPGA is disabled and dummy data is sent by PC. The left window is test result on FPGA console while the right window is test result on Command prompt.
Figure 3‑9 shows the example of receive data test when data verification mode on FPGA is enabled and incremental data is sent by PC. Comparing to Figure 3‑8 that is run without data verification, it can show the better performance. Less PC resource is applied to send dummy data.
Figure 3‑10 shows the example of receive data test when data verification is failed.
Figure 3‑8 Receive data test when data verification is disabled
Figure 3‑9 Receive data test when data verification is enabled
Figure 3‑10 Receive data test when data verification is failed
3.5 Full duplex Test
Select ‘4’ to run full duplex test to transfer data between FPGA and PC in both directions at the same time. User inputs test parameters on FPGA console and PC Command prompts. The user must call two “udpdatatest” applications on two Command prompts by using different port number, one for sending data and another for receiving data. The step to run the test is described as follows.
1) On FPGA console, input three parameters in full duplex test.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit. This value must be equal to total transfer size, set on test application.
ii) Input packet size: Unit of packet size is byte. Valid value is 64 – 8960. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
iii) Input data verification mode: Set ‘0’ to disable data verification or ‘1’ to enable data verification sent from PC.
If all inputs are valid, the recommended parameters to run two applications on PC are displayed, sending data and receiving data. Next, “Press any key to start data transfer ...” is displayed to begin sending data when user enters any key(s).
2) Open two Command prompts to run the applications by using the recommended parameters. Five parameters and one optional parameter are displayed.
Receive data (The 1st command prompt)
>> udpdatatest r [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <Pattern> <Timeout>
Send data (The 2nd command prompt)
>> udpdatatest t [FPGAIP] [FPGAPort] [PCPort] [ByteLen] <Pattern>
i) Dir :
The 1st command prompt : Set ‘r’ to receive data
The 2nd command prompt : Set ‘1’ to send data
ii) FPGA IP : Set the same value as FPGA IP address
iii) FPGA port : Set the same value as FPGA port number
iv) PC port :
The 1st command prompt: Set the same value as target port number (FPGA->Target)
The 2nd command prompt: Set the same value as target port number (Target->FPGA)
v) ByteLen : Set the same value as “Input transfer size” of step 1)
Optional parameters
vi) Pattern : ‘1’- enable data verification, ‘0’-disable data verification.
Default value is ‘1’ which is applied when there is no input.
vii) Timeout : Timeout in msec unit. Valid value is 50-65536.
It is recommended to set 100 for 100Gb speed.
Default value is 100 which is applied when there is no input.
3) On FPGA console, press any key(s) to start sending data to PC. After that, current number of transfer data size in both directions are displayed on FPGA console and two command prompts every second.
4) “Transfer data complete” is displayed on FPGA console after the IP finishes sending and receiving data. Finally, total number of transferred data and performance are displayed.
Figure 3‑11 and Figure 3‑12 show the results when running full duplex by using large data size and small data size respectively. The left window is the test result on FPGA console while the right window is the test result on Command prompt. The upper-right window shows receive performance and the lower-right window shows transmit performance.
Using small data size has better chance to transfer data without lost data but the performance is not good from overhead time and timer resolution limitation on PC test application. While using large data size can detect lost data with higher transfer performance. To show the best performance, data verification should be disabled as shown in Figure 3‑11.
Figure 3‑11 Full duplex test when data is lost
Figure 3‑12 Full duplex test without lost data
4 Test result when using two FPGAs
4.1 Display UDPIP parameters
Select ‘0’ to check current parameter in the demo. There are seven parameters in Client/Server mode or eight parameters in Fixed MAC mode displayed on the console.
Figure 4‑1 Display current parameter result
1) Mode : Set initialization mode of UDP100G-IP to be Server, Client, or Fixed MAC. Input ‘0’ for Client, ‘1’ for Server, or ‘2’ for Fixed MAC.
2) FPGA MAC address : 48-bit hex value to be MAC address of FPGA. Default value is 0x000102030405 (Client and Fixed MAC mode) or 0x001122334455 (Server mode).
3) FPGA IP : IP address of FPGA. Default value is 192.168.100.42 (Client and Fixed mode) or 192.168.100.25 (Server mode).
4) FPGA port number : Port number of FPGA. Default value is 4000 (Client and Fixed MAC mode) or 60000 (Server mode).
5) Target MAC address (displayed when running Fixed MAC mode only) : 48-bit hex value to be MAC address of the target device. Default value is 0x554433221100.
6) Target IP : IP address of the target device. Default value is 192.168.100.25 (Client and Fixed MAC mode) or 192.168.100.42 (Server mode).
7) Target port number (Target->FPGA) : Port number of the target device to receive data. Default value is 61000 (Client and Fixed MAC mode) or 4000 (Server mode).
8) Target port number (FPGA->Target) : Port number of the target device to send data. Default value is 60000 (Client and Fixed MAC mode) or 4000 (Server mode).
To change some parameters, the user runs menu [1] (Reset UDPIP parameters).
Note: When running the test by two FPGA boards, the parameters of two FPGA boards must be matched. Target parameters of the first board must be equal to FPGA parameters of the second board and vice versa.
4.2 Reset UDPIP parameters
Select ‘1’ to change IP parameters or send reset to UDP100G-IP. After user selects this menu, the current parameters are displayed on the console. User enters ‘x’ to use the same parameters while other keys are entered to change some parameters.
There are seven or eight parameters to set in this menu. The parameter is updated to UDP100G-IP when the input is valid. Otherwise, the parameter does not change. After user inputs all parameters, the IP is reset. The description of each parameter is shown in Topic 4.1 (Display UDPIP parameters). The valid range of each parameter is described as follows.
Note:
1. To running two FPGA board test, user can set three different methods for initialization mode on the first board and the second board, i.e., Client – Server, Fixed MAC - Client, and Fixed MAC – Fixed MAC.
2. When user needs to reset parameters on the Server FPGA, the Client FPGA must be also reset. The Server must be reset before the Client to wait until ARP request sent from the Client.
3. The target parameters of the first board must be equal to the FPGA parameters of the second board and vice versa.
4. When running two FPGA board test, Target port number for Target->FPGA and FPGA->Target must be the same value which are equal to FPGA port number of another board.
1) Mode : Input ‘0’ (Client), ‘1’ (Server), or ‘2’ (Fixed MAC) to determine FPGA initialization mode. The conditions of mode setting between 2 FPGA Boards are as follows.
a) If the first board is Client mode, the second board must be Server mode.
b) If the first board is Fixed MAC mode, the second board must be Fixed MAC mode or Client mode.
2) FPGA MAC address : Input 12 digits of hex value. Add “0x” as a prefix to input as hex value.
3) FPGA IP address : A set of four decimal digits is separated by “.”. The valid range of each decimal digit is 0-255.
4) FPGA port number : Valid range is 0-65535.
5) Target MAC address (displayed when running Fixed MAC mode only) : Input 12 digits of hex value. Add “0x” as a prefix to input as hex value.
6) Target IP address : A set of four decimal digits, similar to FPGA IP address on another side.
7) Target port number (Target->FPGA) : Valid range is 0-65535.
8) Target port number (FPGA->Target) : Valid range is 0-65535.
After finishing parameter assignment, new parameter set is displayed on the console. Next, the reset is asserted and the IP starts initialization by using new parameter set. Finally, “IP initialization complete” is shown after IP completes initialization process, as shown in Figure 4‑2 and Figure 4‑3.
Figure 4‑2 Change IP parameter result for Server and Client mode
Figure 4‑3 Change IP parameter result for Fixed MAC mode
4.3 Send and Receive Data Test (Half duplex test)
For half duplex test by using two FPGA boards, one board runs Receive data test (menu 3) while another board runs Send data test (menu 2). User inputs test parameters on FPGA console. The step to run the test is described as follows.
1) On FPGA console which runs menu 3 (Receive data test), input two parameters.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 – 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
ii) Input data verification mode: Set ‘1’ to enable data verification sent by another FPGA.
2) If all inputs are valid, “Wait data from Target ...” is displayed to wait for received data from another FPGA.
3) On FPGA console which runs menu 2 (Send data test), input two parameters.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 – 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
Note: This value must be equal to transfer size, set on step 1).
ii) Input packet size: Unit of packet size is byte. Valid value is 64 – 8960. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
Note: When packet size is more than 1472, the packet output from UDP100G-IP is jumbo frame. User needs to confirm that network device supports jumbo frame when two FPGA boards connect through the network device.
4) If all inputs are valid, “Press any key to start data sending ...” is displayed to begin sending data when user enters any key(s).
5) User enters some key(s) to start data sending and then the data starts transferring. During running the test, current number of transferred data is displayed on both FPGA consoles every second.
6) “Send data complete” is displayed on FPGA console that runs Send data test after finishing sending all data. While “Receive data completed” is displayed on FPGA console that runs Receive data test after finishing receiving all data. Finally, total number of transferred data and transfer performance are displayed on both consoles.
Figure 4‑4 shows the example of half duplex test by using jumbo frame size. The left window is FPGA console running Receive data test while the right window is FPGA console running Send data test. Figure 4‑5 shows the example of half duplex test by using non-jumbo frame size. From the test result, using jumbo frame size achieves the better performance than using non-jumbo frame size.
If some inputs are invalid, “Out-of-range input” is displayed and then the operation is cancelled, as shown in Figure 3‑6 - Figure 3‑7 (similar to FPGA<->PC test).
Figure 4‑4 Half duplex test of two FPGAs by using jumbo frame
Figure 4‑5 Half duplex test of two FPGAs by using non-jumbo frame
4.4 Full duplex Test
Select ‘4’ to run full duplex test on two FPGA boards for transferring data in both directions at the same time and the same port number. User inputs test parameters on FPGA console. The step to run the test is described as below.
1) On the first FPGA console which is initialized by Client mode or Fixed-MAC mode, input three parameters in full duplex test.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
ii) Input packet size: Unit of packet size is byte. Valid value is 64 – 8960. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
iii) Input data verification mode: Set ‘1’ to enable data verification to verify data from the second FPGA.
2) If all inputs are valid, “Press any key to start data transferring ...” is displayed.
3) On the second FPGA console which is initialized by Fixed-MAC mode or Server mode, input three parameters in full duplex test.
i) Input transfer size: Unit of transfer size is byte. Valid value is 64 - 0xFFFF_FFFF_FFC0. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
Note: This input must be set by the same value as step 1).
ii) Input packet size: Unit of packet size is byte. Valid value is 64 – 8960. The input must be aligned to 64. The input is decimal unit when input only digit number. User adds “0x” to be a prefix for hexadecimal unit.
iii) Input data verification mode: Set ‘1’ to enable data verification to verify data from the first FPGA.
4) If all inputs are valid, the next message will be displayed following the initialization mode.
a) If the second FPGA is initialized by Fixed-MAC mode, “Press any key to start data transferring ...” will be displayed. User enters the key(s) to start full duplex test on the first FPGA console and the second FPGA console.
b) If the second FPGA is initialized by Server mode, “Wait data from Target” will be displayed. User enters the keys(s) to start full duplex test on the first FPGA console only.
5) The data starts transferring. Current number of transferred data is displayed on both FPGA consoles every second.
6) “Transfer data complete” is displayed on both FPGA consoles after finishing transferring all data. Finally, total number of transferred data and performance are displayed on both FPGA consoles.
Figure 4‑6 and Figure 4‑7 show full duplex test by using two FPGA boards when running jumbo frame and non-jumbo frame respectively. Similar to half duplex test, the performance by using jumbo frame is higher than using non-jumbo frame.
Figure 4‑6 Full duplex test when using jumbo frame
Figure 4‑7 Full duplex test when using non-jumbo frame
5 Revision History
|
Revision |
Date |
Description |
|
1.0 |
5-Aug-21 |
Initial version release |
|
1.1 |
18-Aug-21 |
Update test performance with TestPC |