tCAMIP reference design by Search Replace function

Rev1.00　 1-Sep-2023

1    Introduction. 1

2    Hardware overview. 1

2.1    Search Replace module. 2

2.1.1    Search Table. 2

2.1.2    Initial State Machine. 4

2.1.3    Replace Table. 5

2.1.4    tCAMIP searching process. 6

3     Test Logic. 7

4     Revision History. 8

 

 

1       Introduction

This document describes the detail of tCAMIP reference design. In this reference design, tCAMIP are used for search/replace function. More details of the hardware design are described as follows.

 

2       Hardware overview

 

Figure 2‑1 Reference design block diagram

 

In this test environment, the SearchReplace module comprises a tCAMIP along with two simple dual-port RAMs functioning as a search table and a replace table, respectively. The system incorporates Test Logic to control the operation of the entire system. LEDs are employed to indicate the working status.

 

2.1     Search Replace module

Search Replace module is designed to search 64-bit dataIn in Search Table. When dataIn is matched in Search Table, dataOut is assigned with replace word from Replace Table. But if dataIn is not matched in Search Table (resultData=0), the dataIn is assigned to dataOut instead.

 

2.1.1   Search Table

Search Table is dual port RAM, 8K address x 9-bit width. This table is assigned to be rule table for tCAMIP.

Port A is reserved for future used.

Port B is connected with tCAMIP as shown in Table 2‑1.

ruleCount(3) is designed to generate 1 clock cycle pulse delay from ruleRdReq signal and is assigned to be ruleRdValid signal. Figure 2‑2 show timing diagram of ruleRdValid generation.

 

Table 2‑1 Port B signal mapping of search table

 

 

Figure 2‑2 Timing diagram of ruleRdValid generation

 

Each 8-byte ASCII code of search word is assigned as 8 x 9-bit rule. The “don’t care” byte is assigned as [x], 0x100 value. Table 2‑2 shows sample conversion from search word to rule table. Search Table is initialed values with file “search.mif”.

 

Table 2‑2 Sample of search word conversion to rule table memory

Note: All numbers are hex number.

 

2.1.2   Initial State Machine

This reference design is provided simple state machine to initialize tCAMIP. Figure 2‑3 show timing diagram of Initial State Machine to generate ruleInit signal and check ruleBusy and ruleStatusCode signals. Operation of initialization is described as below.

·       When RstB is active (‘0’), rState is set to stIdle.

·       When RstB is released (‘1’), rState is changed to stInitStart.

·       At stInitStart, rState is changed to stWaitReady when ruleBusy is active from tCAMIP.

·       At stWaitReady, rState is changed to stInitCompleted when ruleBusy is released to zero and ruleStatusCode is 0001b (initial completed).

o   In case that ruleBusy is released to zero but ruleStatusCode is not 0001b, it means tCAMIP initialization is not success. rState is changed to stIdle for restart initial process again.

 

 

Figure 2‑3 Timing diagram of Initial State Machine

 

2.1.3   Replace Table

Replace Table is dual port RAM, 1K address x 64-bit width. This table is assigned with replace word. The relation between search word, replace word and memory data is shown as in Table 2‑4. Replace Table is initialed values with file “replace.mif”. For further details and all related parameters, please refer to the file "SampleTable.txt".

According to resultData from tCAMIP is mapping with Rule No., then address of replace word can be calculated by resultData minus 1 (rep_address_b <= resultData – 1). The detailed of signals assignment is shown as below.

Port A is reserved for user logics.

Port B is connected with signals as shown in Table 2‑3.

 

Table 2‑3 Port B signal mapping of replace table

Table 2‑4 Sample of search word conversion to rule table memory

 

2.1.4   tCAMIP searching process

Figure 2‑4 shows timing diagram of searching data path. After tCAMIP initialization is completed by initial process on topic 2.1.2, In every clock cycle, dataIn will be searching by tCAMIP and set resultData as matched Rule No. by latency 7 clock cycles. rep_address_b (resultData – 1) from tCAMIP is used for address of Replace Table, then rep_q_b is out from Replace Table after 2 clock cycles because Replace Table memory is generated with both registers of input address port and output port. rSearchMatch(0) is set to ‘1’ when resultData from tCAMIP is zero (not match). Then rSearchMatch(1) is one clock cycle delay from rSearchMatch(0). To control timing of input dataIn and rep_q_b in the same clock cycle, dataIn8 is 9 clock cycles delay from dataIn signals, then dataIn8 and rep_q_b is valid in the same clock cycle. rLongWord is set to be ‘1’ when previous cycle of dataIn8[63:56] (last byte of word) is 0x20 (space bar character). Then dataOut is register output multiplexer that is assigned with rep_q_b when rLongWord=’0’ and rSearchMatch(1)=’1’, else is assigned with dataIn8.

 

 

Figure 2‑4 Timing diagram of searching data path

 

3       Test Logic

For testing, the Search Replace module uses Test Logic to generate dataInValid and dataIn for use as input data to Search Replace module, and validate the output of the Search Replace module. Test Logic will display the operation status through LED. The definition of LED is shown in the Table 3‑1.

 

Table 3‑1 LED Definition

 

Figure 3‑1 Example test logic operation timing diagram, after tCAMIP initialization is completed by initial process on topic 2.1.2. Ready signal is asserted to ‘1’, then rCnt[15:0] will be started to count. When rCnt[8:4] is 0x01, dataInValid is asserted to ‘1’ for 16 clock cycles, and dataIn[63:0] is valid by selecting from rPattern data. Then dataOutValid will be active ? clock cycles after dataInValid, So we prepare rResult data pattern and result[63:0] for compare with dataOut[63:0] to show the correct operation of tCAM-IP.

However in case of something wrong, such as dataOut is not same as rResult data pattern, the rError signal is asserted to ‘1’ and will be active LED[2] to show error status.

 

 

Figure 3‑2 Example test logic operation when dataOut not match result

 

4       Revision History