tCAM-IP Core Datasheet
· Rule Table memory initialize value
· Rule Initialize control signals
Core Facts |
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Provided with Core |
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Documentation |
User Guide, Design Guide |
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Design File Formats |
Encrypted File |
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Instantiation Templates |
VHDL |
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Reference Designs & Application Notes |
Vivado Project, See Reference design manual |
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Additional Items |
Demo on KCU116 |
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Support |
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Support Provided by Design Gateway Co., Ltd. |
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Design Gateway Co., Ltd
E-mail: ip-sales@design-gateway.com
URL: design-gateway.com
Features
· Key width 64/56/48/40/32/24 bits
· Up to 64K/128K/256K/512K/1M rule entries
· Searching latency is constant at 7 clock cycles
· Up to 300 MSPS @ 300MHz searching speed
· Easy to customize rule table memory
· Simple rule table memory setup and user interface signals
Customizable
· Extend max rule width bits
· Extend max rule entries
· To support external memory
Table 1 Example Implementation Statistics for tCAM-IP up to 256K rule entries
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Family |
Example Device |
Fmax (MHz)
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CLB Regs
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CLB LUTs
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CLB1 |
IOB |
BRAMTile |
Design Tools |
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Kintex UltraScale+ |
XCKU5P-FFVB676-2-E |
300 |
967 |
1201 |
297 |
- |
149.5 |
Vivado2022.1 |
Notes:
1) The actual logic resource depends on the percentage of unrelated logic.
Figure 1 tCAM-IP Block Diagram
Applications
tCAM-IP is content addressable memory based on FPGA, that provides extremely low latency matching function at 300MSPS (million samples per second) continuously matching speed. It can achieve 300 M-Packet/sec (million packets per second) filtering on 100Gbps Ethernet.
General Description
tCAM-IP requires a simple initialization process, which is described in the following sections. After tCAM-IP analyzes the rule data table and initializes the internal matching logics. When initialization process is completed, tCAM-IP can continuously pass key to searching @300MSPS, and send matching result with fixed 7 clock cycles latency from key.
Functional Description
The tCAM-IP core can be divided into three parts as follows: rule table memory interface signals, rule initialization control signals, and key searching signals.
Table 2 Core Parameters
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Parameter name |
Value |
Description |
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MAX_RULE |
16-20 |
Setting number of maximum rules (2^MAX_RULE). |
Table 3 Interface signals of tCAM-IP
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Signal name |
Dir |
Description |
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RstB |
In |
IP core system reset. Active low. |
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Clk |
In |
IP core system clock. |
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version[31:0] |
Out |
32-bit version number of IP. |
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Rule table memory interface signals |
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ruleAddr[31:0] |
Out |
ruleAddr is 32-bit address signal, that tCAM-IP sends to memory in first clock of read cycle, and holds value until getting ruleRdValid=1 from memory module. |
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ruleRdReq |
Out |
ruleRdReq is request signal, that tCAM-IP sends logic 1 to memory in first clock of read cycle, and holds 1 until getting ruleRdValid=1 from memory module. |
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ruleRdValid |
In |
ruleRdValid is data valid signal, that memory module set to 1, one clock when ruleData is valid. |
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ruleData[8:0] |
In |
ruleData is read data signal, that memory module returns data in memory to tCAM-IP. |
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Rule initialize control signals |
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ruleWidth[15:0] |
In |
ruleWidth is 16-bit value to specify number bits of rule. tCAM-IP can support 64/56/48/40/32/24 bit width. |
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ruleCount[31:0] |
In |
ruleCount is 32-bit value to specify number of rules to initialize tCAM-IP for searching. |
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ruleInit |
In |
ruleInit is request signal, sent to tCAM-IP to start initialization process. tCAM-IP will keep ruleWidth and ruleCount value in the first clock of ruleInit=1 and use for initialization process. |
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ruleBusy |
Out |
ruleBusy is set to 1 when tCAM-IP detects ruleInit=1, and ruleBusy remains 1 until the initialization process is finished, after which tCAM-IP will set ruleBusy to 0. |
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ruleStatusCode[3:0] |
Out |
ruleStatusCode is shown initialization status of tCAM-IP. User can read this signal when initialization process is finished. (ruleBusy is changed from 1 to 0) |
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Key searching signals |
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keyValid |
In |
keyValid is user signal to specify data valid of keyData. |
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keyData[63:0] |
In |
keyData is 64-bit key data of searching. tCAM-IP can continuously search every clock cycle. |
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resultValid |
Out |
resultValid specifies data valid for resultData, tCAM-IP generates resultValid signal from keyValid with 7 clock cycles latency. |
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resultData[31:0] |
Out |
resultData is the 32-bit result data of the searched key. resultData has a fixed latency of 7 clock cycles from keyData. |
· Rule Table memory interact
tCAM-IP is designed to separate rule table memory that is more flexible to customize by user. User may use simple memory IP or use external memory, such as SD-RAM or DDR-RAM.
Rule table memory interface signals is simple memory interface. Figure 2 shows timing diagram of rule table memory interface signals, user can simple customize memory latency time by delay ruleRdValid signal.
Figure 2 Rule Table memory interface timing diagram
· Rule Table memory initialize value
Rule Table memory is designed based on 9-bit data width memory, because rule value range is 0 to 255 and 256 for dont care.
In the first step of initialization process, the user needs to set all value in the rule table memory before send rule initialize control signals. Figure 3 shows example of memory address mapping from user rule data for 64-bit width rule. The maximum memory required is 2048K x 9-bit for up to 256K rule combinations.
Figure 3 Example of Rule Table initialize values for 64-bit width rule
Figure 4 shows example of memory address mapping from user rule data for 32-bit width rule. The maximum memory requires 1024K x 9-bit for maximum 256K rules combination.
Figure 4 Example of Rule Table initialize values for 32-bit width rule
Figure 5 shows example of memory address mapping for 24-bit width rule. The maximum memory requires 1536K x 9-bit for maximum 512K rules combination.
Figure 5 Example of Rule Table initialize values for 24-bit keys
Priority of searching process is based on ascending sequence of rules in rule table memory. For more understanding about priority, examples of searching key and result based on Figure 4 is shown as below.
l When searching key is 192.168.10.30, the result is rule no. 7.
l When searching key is 192.168.20.30, the result is rule no. 10.
l When searching key is 192.100.10.30, the result is rule no. 12.
l When searching key is 111.111.111.111, the result is rule no. 0 (0 is default value of rule x.x.x.x).
· Rule Initialize control signals
The user can specify ruleWidth as the number of bits per rule (64/56/48/40/32/24) and ruleCount as the number of rules. Then set ruleInit signal to 1. The tCAM-IP will acknowledge ruleInit signal by set ruleBusy to be 1. The tCAM-IP will take some time to analyze and prepare internal matching parameters; initialization time depends on the ruleWidth and ruleCount values. When initialize process is finished, tCAM-IP will set ruleStatusCode before pulling ruleBusy signal to be 0 as shown in Figure 6
Figure 6 Rule initialize control signals timing diagram
ruleStatusCode meaning is shown as below.
0 : no initialize yet. (after power or hardware reset state)
1 : initialize completed.
2 : error with ruleCount is over maximum number of rules.
3 : error with rule value patterns are generated over maximum number of CAM.
4 : error with unsupported ruleWidth (must be 64, 56, 48, 40, 32, or 24 bits).
5 : error with MAX_RULE out of bounds (less than 16 or greater than 20).
When user detects ruleStatusCode is 2, 3, 4, or 5, tCAM-IP is not ready for searching. User can retry initialize again by changing ruleWidth, ruleCount and setting ruleInit to 1 for restarting initialization process again.
After the initialization process is finished with ruleStatusCode=1, tCAM-IP can continuously search keys every clock cycle by result has fixed latency at 7 clock cycles.
· Key searching signals
After rule initialization process is completed, user can continuously send key to search in tCAM-IP. resultValid signal is provided to easy control signal for matching between key and result as shown in Figure 7
Figure 7 Key searching signals timing diagram
Example usage
The example sequence to initial tCAM-IP is shown as Figure 8
Figure 8 User operation flow
1) Users can reset tCAM-IP by set RstB = 0
2) Users prepare all rule values in rule table memory
3) Users start to initial tCAM-IP by
a. set ruleInit=1 while ruleWidth and ruleCount are valid values.
b. wait until ruleBusy=0, and check ruleStatusCode. If ruleStatusCode is not 0x1, redo from Step 2)
4) User can continuously send key to search, and result will come out with 7 clock cycles latency.
Limitation
· Maximum number of rules is up to rule pattern optimization. In the most of patterns, tCAM-IP can fit less than 2^MAX_RULE rules.
Verification Methods
The tCAM-IP Core functionality was verified by simulation and also proved on real board design by using KCU116 development board.
Recommended Design Experience
The user must be familiar with HDL design methodology to integrate this IP into a system.
Ordering Information
This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. For pricing and additional information about this product, use the contact information on the front page of this datasheet.
Revision History
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Revision |
Date (D-M-Y) |
Description |
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2.00 |
3-Oct-24 |
- Improve design to reduce initialization time. - Add more error codes and validators. |
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1.00 |
3-Aug-21 |
New release |