100GbE TCP Off-loading Engine(TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE100G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE100G-IP core on real board before purchasing.
|Support Devices||Agilex F-Series, Stratix®10 MX|
|IP core &
|Datasheet||Reference Design Document||Demo Instruction||FPGA Board Set up Document||Evaluation file Get Password|
Stratix 10 GX