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TOE100G-IP coreAvailable on Agilex F series!!

TOE100G-IP

100GbE TCP Off-loading Engine(TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE100G-IP core on real board before purchasing.

Features

  • TCP/IP off-loading engine for 100Gbit Ethernet
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 512-bit, transmitted data bus size
  • Total receive data size aligned to 512-bit, received data bus size
  • Simple data interface by standard FIFO interface at 512-bit data bus
  • Simple control interface by single-port RAM interface
  • 512-bit Avalon stream interface with 100G Ethernet MAC
  • At least 220 MHz user clock frequency
  • Provide free evaluation sof file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product


Block diagram



Document & Demo file download

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Support Devices Agilex F-Series, Stratix®10 MX
IP core &
Option
Datasheet Reference Design Document Demo Instruction FPGA Board Set up Document Evaluation file Get Password
TOE100G-IP Rev1.0 Rev1.0 Rev1.0 Rev1.0 Agilex F
Stratix 10 GX


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