100GbE TCP Offloading Engine(TOE100G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE100G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE100G-IPcore on real board before purchasing.
|TOE100G-IP core Presentation||coming soon|
|TOE100G-IP core Introduction Video|
|Support Devices||Virtex UltraScale+ VCU118, Kintex UltraScale+ KCU116
|IP core & Option||Datasheet||Reference Design Document||Demo Instruction Document||FPGA Board Set up Document||Evaluation demo file ask password|