The Expert of IP Core & Embedded

100GbE TCP Offloading Engine(TOE100G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE100G-IPcore on real board before purchasing.

Features

• All pure hardware TCP/IP protocol stack
• Support IPv4 protocol
• Support one port connection (Support Multi-session by implementing multiple cores)
• Supports Full Duplex communication
• Support both Server and Client mode (Passive/Active open and close)
• Support Jumbo frame
• Transmitted packet size aligned to 512-bit, bus size of transmit data
• Total received data size aligned to 512-bit, bus size of received data
• Simple data interface by standard FIFO interface
• Simple control interface by single port RAM interface
• 512-bit AXI4 stream interface with 100G Ethernet MAC
• At least 240 MHz user clock frequency
• Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
• Reference design is included in IP core product

Block diagram

Document & Demo bit file download

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Document Name	Revision
TOE100G-IP core Presentation	coming soon
TOE100G-IP core Introduction Video

Support Devices	Virtex UltraScale+ VCU118, Kintex UltraScale+ KCU116
IP core & Option	Datasheet	Reference Design Document	Demo Instruction Document	FPGA Board Set up Document	Evaluation demo file ask password
TOE100G-IP	Rev1.1	Rev1.0	Rev1.0	Rev1.1	U250 KCU116 Silicom KU15P