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TOE10G-IP coreSupport Intel®PAC

TOE10G-IP

10GbE TCP Off-loading Engine(TOE10G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE10G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE10G-IP core on real board before purchasing.

Features

  • 10GbE TCP/IP stack implementation
  • Support IPv4 protocol
  • Support one port connection
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 156.25 MHz clock frequency
  • Super low-latency DG 10G EMAC-IP for TOE10G-IP core (Option) Learn more
  • Support Multi-session (8 Sessions Reference design is available)
  • Provide free evaluation demo file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram



Document & Demo file download

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Document Name Revision
TOE10G-IP core Presentation Rev1.2AE
DG EMAC-IP Presentation Rev1.0AE
Support Devices Intel®PAC, Stratix® 10 GX, Arria® 10 SX, Arria® 10 GX, Cyclone® 10 GX
IP core & Option Datasheet Reference Design Document Demo Instruction Document FPGA board Setup Evaluation demo file ask password Demo Video
TOE10G-IP Rev1.7 Rev1.3

Rev1.0 (PAC)
Rev2.1

Rev1.0 (PAC)
Rev3.1 Intel PAC
Stratix 10 GX
Stratix 10 MX
Arria 10 SX
Arria 10 GX

Cyclone 10 GX

Intel PAC


Arria 10 SX
10G EMAC-IP Rev1.1 Rev1.0 Rev1.0 Cyclone 10 GX
Multi Session Rev1.0 Rev1.0 Arria 10 SX


Super low-latency DG 10GbE MAC core for TOE10G-IP

DG 10GbE MAC core implements the MAC layer for TOE10G-IP core and fully compatible with Intel MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage, ? of Intel MAC core.
  • Very low price, 1/5 of Intel MAC core.

DG 10GEMAC-IP Intel 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 76.8ns (12clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 83.2ns (13clk)
ALMs 1362 1617
Registers 1259 3015
Block Memory 0 2320

Support Multi-Session!!


TOE10G-IP core is compact resource. It achieves multi-session by implementing multiple cores in FPGA. Total performance does not drop even the number of sessions increases.
You can free evaluate TOE10G 8 session demo bit file on Intel FPGA boards.





Free sof file for evaluation to able to see the performance

DesignGateway provide 1-hour limitation sof file for Arria10 SoC FPGA Development Kit. You can evaluate TOE10G-IP core on real board before purchasing.








Application example

TOE10G-IP core is the vest solution for large-scale and high-speed data transmission applications such as image/video streaming or data storage
Large scale Blade Server NAS SDN (Software Defined Network) Video Editing System


Specification Comparison of TOE-IP series and how to choose suitable solution for your application : Click Here

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