10GbE TCP Off-loading Engine(TOE10G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE10G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate
TOE10G-IP core on real board before purchasing.
Document Name | Revision |
TOE10G-IP core Presentation | Rev1.2AE |
DG EMAC-IP Presentation | Rev1.0AE |
Support Devices | Intel®PAC, Stratix® 10 GX, Arria® 10 SX, Arria® 10 GX, Cyclone® 10 GX | |||||
IP core & Option | Datasheet | Reference Design Document | Demo Instruction Document | FPGA board Setup | Evaluation demo file ask password | ![]() |
TOE10G-IP | Rev1.7 | Rev1.3 Rev1.0 (PAC) |
Rev2.1 Rev1.0 (PAC) |
Rev3.1 | Intel PAC Stratix 10 GX Stratix 10 MX Arria 10 SX Arria 10 GX Cyclone 10 GX |
![]() Intel PAC ![]() Arria 10 SX |
10G EMAC-IP | Rev1.1 | Rev1.0 | Rev1.0 | Cyclone 10 GX | ||
Multi Session | Rev1.0 | Rev1.0 | Arria 10 SX |
DG 10GbE MAC core implements the MAC layer for TOE10G-IP core and fully compatible with
Intel MAC. It has many advantages.
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DG 10GEMAC-IP | Intel 10GEMAC | |
Tx latency (clk freq.=156.25MHz) | 19.2ns (3clk) | 76.8ns (12clk) |
Rx latency (clk freq.=156.25MHz) | 44.8ns (7clk) | 83.2ns (13clk) |
ALMs | 1362 | 1617 |
Registers | 1259 | 3015 |
Block Memory | 0 | 2320 |
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Large scale Blade Server | NAS | SDN (Software Defined Network) | Video Editing System |