TCP Offloading Engine(TOE) 1G IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE1G-IP built by pure hardwired logic can take place of such
extra CPU for TCP protocol management. This IP product includes reference
design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA Development Kit for evaluation. You can evaluate TOE1G-IP core on real board before purchasing.
Specification Comparison of TOE-IP series and how to choose suitable solution for your application: Click Here
|TOE1G-IP core Presentation||Rev1.4|
|Devices||Arria® 10 SX, Cyclone® 10 GX, Arria® V GX, Cyclone® V E, Stratix® IV GX|
|Datasheet||Reference Design Document||Demo Instruction Document||FPGA Setup Document||Evaluation sof file Get Password||Demo Video|
& CPU demo
|Rev2.10||Rev1.1||Rev1.2||Rev2.0||Arria 10 SX
Arria V GX
|2 port demo||Rev1.0||Rev1.0||Cyclone 10 GX|
|FTP Server demo with SATA-IP & exFAT-IP||Rev1.0||Rev1.0||Cyclone 10 GX|