TCP Offloading Engine(TOE) 1G IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE1G-IP built by pure hardwired logic can take place of such
extra CPU for TCP protocol management. This IP product includes reference
design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE1G-IP core on real board before purchasing.
|Document name||Update (Revision)|
|TOE1G-IP core Presentation||1.1|
|Devices||Zynq-7000 ZC706, Virtex-7 VC707, Kintex-7 KC705, Artix-7 AC701|
|Datasheet||Reference Design Document||Demo Instruction Document||FPGA Board Setup||Evaluation bit file & Apps for PC Get Password||Demo Video|
& CPU demo
|2 port demo||Rev1.3||Rev1.2||ZC706
|FTP server demo with SATA-IP||Rev1.1||Rev1.1||ZC706