25GbE TCP Off-loading Engine(TOE25G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE25G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE25G-IP core on real board before purchasing.
|TOE25G-IP core Presentation||coming soon|
|IP core Introduction Video|
|IP core Performance Demo Video||
Stratix 10 GX
|Document Name||Arria®10 GX|
|TOE25G-IP core Datasheet||Rev1.0|
|Reference Design Document||Rev1.0|
|Demo Instruction Document||Rev1.1|
|FPGA Board Set up Document for TOE25G-IP demo||Rev1.0|
|Evaluation file & Apps for PC
|Arria 10 GX|