本文へスキップ

The Expert of IP Core & Embedded

TOE25G-IP coreprovides 2.5X the performance of 10GbE over single channel

TOE25G-IP

25GbE TCP Off-loading Engine(TOE25G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE25G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE25G-IP core on real board before purchasing.


Features

  • TCP/IP off-loading engine for 25Gbit Ethernet
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 128-bit, bus size of transmit data
  • Total received data size aligned to 128-bit, bus size of received data
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by 128-bit FIFO interface
  • Simple control interface by 32-bit Register interface
  • 64-bit to interface for 10G/25G Ethernet MAC
  • Support 10GbE by using DG 10GbEMAC-IP
  • Provide free evaluation sof file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram



Document & Demo file download

Please receive technical document update from DG News Letter. Subscribe to DG News
Document Name Revision
TOE25G-IP core Presentation coming soon
IP core Introduction Video
IP core Performance Demo Video
Stratix 10 GX
Document Name Arria®10 GX
TOE25G-IP core Datasheet Rev1.0
Reference Design Document Rev1.0
Demo Instruction Document Rev1.1
FPGA Board Set up Document for TOE25G-IP demo Rev1.0
Evaluation file & Apps for PC
Get Password
Arria 10 GX


Support Multi-Session!!


TOE25G-IP core is compact resource. It achieves multi-session by implementing multiple cores in FPGA. Total performance does not drop even the number of sessions increases.






Alliance Partner



Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/13 Amornpan 205 Tower1, 11th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND