25GbE TCP Offloading Engine(TOE25G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE25G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE25G-IPcore on real board before purchasing.
|TOE25G-IP core Presentation||coming soon|
|IP core Introduction Video|
VCU118 / KCU116
|TOE25G-IP core Datasheet||Rev1.2|
|Reference Design Document||Rev1.2|
|CPU Demo Instruction Document||Rev1.1|
|FPGA Board Set up Document for TOE25G-IP demo||Rev1.1|
|Evaluation bit file & Apps for PC
|10G25G EMAC-IP core Datasheet||Rev1.3|