40GbE TCP Offloading Engine(TOE40G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU
is required. TOE40G-IP built by pure hardwired logic can take place of
such extra CPU for TCP protocol management. This IP product includes reference
design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE40G-IPcore on real board before purchasing.
|TOE40G-IP core Presentation||Rev1.0XE|
|Document Name||Kintex Ultrascale / Zynq Ultrascale+
KCU105 / ZCU102 / ZCU106
|TOE40G-IP core Datasheet||Rev1.1|
|Reference Design Document||Rev1.0|
|Demo Instruction Document||Rev1.2|
|Evaluation bit file & Apps for PC
|Large scale Blade Server||NAS||SDN (Software Defined Network)||Video Editing System|