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The Expert of IP Core & Embedded

UDP10G-IP coreUDP/IP stack implementation by all hardware logic, without CPU

UDP10G-IP

UDP10G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.


Features

  • All hardware logic to achive CPU-less system
  • Support IPv4 protocol
  • Support one port connection
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 125 MHz clock frequency
  • Multicast/broadcast Tx feature customization
  • Super low-latency DG 10G EMAC-IP for UDP10G-IP core (Option) Learn more
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Rerference design is included in IP core product


Block diagram




Document & Demo bit file download

Common Documents

Document name Revision
UDP10G-IP core Presentation 1.1E
DG EMAC-IP Presentation Rev1.0

Document Name Ultrascale / 7-Series
UDP10G-IP core Datasheet Rev1.1
Reference Design Document Rev1.2
Demo Instruction Document Rev1.1
Evaluation bit file & Apps for PC Get Password KCU105 / ZCU102
Demo Video
10GEMAC-IP for UDP10G-IP Datasheet Rev1.0


Super low-latency DG 10GbE MAC core for UDP10G-IP

DG 10GbE MAC core implements the MAC layer for UDP10G-IP core and highly compatible with Xilinx MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage, ½ of Xilinx MAC core.
  • Very low price, 1/5 of Xilinx MAC core.

DG 10GEMAC-IP Xilinx 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 19.2ns (3clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 115.2ns (18clk)
CLB LUTs 1873 3498
CLB Registers 1072 3291
CLB 326 694

Free bit file for evaluation

DesignGateway provide 1-hour limitation bit file for Xilinx FPGA Development Boards. You can evaluate UDP10G-IP core on real board before purchasing.


Alliance Partner


Design Gateway Co., Ltd.

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