{"id":302,"date":"2021-06-25T13:24:33","date_gmt":"2021-06-25T04:24:33","guid":{"rendered":"https:\/\/dgway.com\/blog\/?p=302"},"modified":"2021-06-25T13:36:23","modified_gmt":"2021-06-25T04:36:23","slug":"nvme-ip-series","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog\/2021\/06\/nvme-ip-series\/","title":{"rendered":"CPU\u30ec\u30b9 NVMe-IP \u306e \u591a\u7a2e\u591a\u5f69\u306a\u30e9\u30a4\u30f3\u30ca\u30c3\u30d7"},"content":{"rendered":"\n

\u30c7\u30b6\u30a4\u30f3\u30fb\u30b2\u30fc\u30c8\u30a6\u30a7\u30a4\u3067\u306f\u3001\u69d8\u3005\u306a\u30b7\u30b9\u30c6\u30e0\u8981\u4ef6\u304a\u3088\u3073FPGA\u30c7\u30d0\u30a4\u30b9\u4ed5\u69d8\u306b\u5bfe\u5fdc\u3059\u308bNVMe IP\u30b3\u30a2\u3092\u63d0\u4f9b\u3057\u3066\u304a\u308a\u307e\u3059\u3002\u3053\u3053\u3067\u306f\u5404\u30e9\u30a4\u30f3\u30ca\u30c3\u30d7\u306e\u7279\u9577\u306b\u3064\u3044\u3066\u8aac\u660e\u3057\u307e\u3059\u3002<\/p>\n\n\n\n

NVMe-IP \u30b3\u30a2\u30b7\u30ea\u30fc\u30ba \u30e9\u30a4\u30f3\u30ca\u30c3\u30d7<\/h4>\n\n\n\n
NVMe-IP<\/strong><\/td>raNVMe-IP<\/strong><\/td>NVMe-IP-SW<\/strong><\/td>NVMeG3-IP\/NVMeG4-IP<\/strong><\/td><\/tr>
\u6a19\u6e96\u7248<\/td>\u30e9\u30f3\u30c0\u30e0\u30fb\u30a2\u30af\u30bb\u30b9\u5bfe\u5fdc<\/td>PCIe\u30b9\u30a4\u30c3\u30c1\u5bfe\u5fdc<\/td>PCIe Soft IP \u5185\u8535\u7248<\/td><\/tr>
\u8d85\u9ad8\u901f\u30b7\u30fc\u30b1\u30f3\u30b7\u30e3\u30eb\u30fb\u30a2\u30af\u30bb\u30b9\u3092\u8981\u6c42\u3059\u308b\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u306b\u6700\u9069
PCIe Hard IP\u63a5\u7d9a<\/strong>\u3067\u30b3\u30f3\u30d1\u30af\u30c8\u30fb\u30ea\u30bd\u30fc\u30b9<\/td>		500K IOPS \u8d85<\/strong>\u306e\u30e9\u30f3\u30c0\u30e0\u30fb\u30e9\u30a4\u30c8\u30fb\u30a2\u30af\u30bb\u30b9
\u591a\u304f\u306e\u975e\u9023\u7d9a\u9818\u57df\u306b\u30c7\u30fc\u30bf\u306e\u30ea\u30fc\u30c9\u30fb\u30e9\u30a4\u30c8\u3092\u8981\u6c42\u3059\u308b\u30b7\u30b9\u30c6\u30e0\u306b\u6700\u9069<\/td>		PICe \u30b9\u30a4\u30c3\u30c1<\/strong>\u30dc\u30fc\u30c9\u3092\u4ecb\u3057\u3001\u5927\u5bb9\u91cf\uff06\u30b9\u30b1\u30fc\u30e9\u30d6\u30eb\u306a\u30b9\u30c8\u30ec\u30fc\u30b8\u30fb\u30b7\u30b9\u30c6\u30e0\u3092\u5b9f\u73fe<\/td>PCIe Hard IP \u304c\u672a\u642d\u8f09\u3001\u3042\u308b\u3044\u306f\u5c11\u306a\u3044\u30c7\u30d0\u30a4\u30b9\u306b\u6700\u9069\u3002PCIe Gen3 \u7248\u3068Gen4\u7248<\/strong>\u3092\u7528\u610f<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

NVMe-IP (\u6a19\u6e96\u7248)<\/h4>\n\n\n\n
\"\"
NVMe-IP \u30b3\u30a2\u306f\u5b8c\u5168\u30cf\u30fc\u30c9\u30ed\u30b8\u30c3\u30af\u3001CPU\u3001OS\u5916\u90e8\u30e1\u30e2\u30ea\u4e0d\u8981\u3001\u30b7\u30f3\u30d7\u30eb\u306a\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30fc\u30b9\u3067\u4f7f\u3044\u3084\u3059\u304f\u3001\u7701\u30ea\u30bd\u30fc\u30b9<\/figcaption><\/figure><\/div>\n\n\n\n

raNVMe-IP (\u30e9\u30f3\u30c0\u30e0\u30a2\u30af\u30bb\u30b9\u5bfe\u5fdc\u7248)<\/h4>\n\n\n\n
\"\"
\u975e\u9023\u7d9a\u30c7\u30fc\u30bf\u306e\u30ea\u30fc\u30c9\u30fb\u30e9\u30a4\u30c8\u3001\u30c7\u30fc\u30bf\u9577\u304c\u4e0d\u5b9a\u306a\u30c7\u30fc\u30bf\u306e\u8a18\u9332\u3001\u8907\u6570\u30e6\u30fc\u30b6\u30fc\u304b\u3089\u306e\u30a2\u30af\u30bb\u30b9\u306b\u5bfe\u5fdc<\/figcaption><\/figure><\/div>\n\n\n\n

NVMe-IP-SW (PCIe\u30b9\u30a4\u30c3\u30c1\u5bfe\u5fdc\u7248)<\/h4>\n\n\n\n
\"\"
PCIe\u30b9\u30a4\u30c3\u30c1\u30ab\u30fc\u30c9\u3092\u4ecb\u3057\u30011\u3064\u306eNVMeSW-IP\u3067\u8907\u6570SSD\u306b\u30a2\u30af\u30bb\u30b9\u53ef\u80fd<\/figcaption><\/figure><\/div>\n\n\n\n

NVMeG3-IP \/ NVMeG4-IP (PCIe Soft IP\u5185\u8535\u7248)<\/h4>\n\n\n\n
\"\"
\u30c7\u30d0\u30a4\u30b9\u306ePCIe Hard IP \u6570\u306b\u4f9d\u5b58\u3057\u306a\u3044\u3001\u5185\u8535\u30c8\u30e9\u30f3\u30b7\u30fc\u30d0\u3092\u6700\u5927\u9650\u5229\u7528\u3057\u305f\u30de\u30eb\u30c1\u30fb\u30c1\u30e3\u30cd\u30ebRAID\u69cb\u7bc9\u304c\u53ef\u80fd
\u5c02\u7528\u306b\u8a2d\u8a08\u3055\u308c\u305fPCIe Soft IP \u306b\u3088\u308a\u3001\u30ea\u30bd\u30fc\u30b9\u6d88\u8cbb\u3092\u5927\u5e45\u524a\u6e1b<\/figcaption><\/figure><\/div>\n\n\n\n

\u307e\u3068\u3081<\/h4>\n\n\n\n