{"id":1381,"date":"2023-08-01T09:00:00","date_gmt":"2023-08-01T02:00:00","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=1381"},"modified":"2023-08-02T09:11:50","modified_gmt":"2023-08-02T02:11:50","slug":"achieving-beyond-7gb-s-transfer-speeds-on-nvme-gen4-ssd-with-next-generation-fpga-ip-core","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2023\/08\/01\/achieving-beyond-7gb-s-transfer-speeds-on-nvme-gen4-ssd-with-next-generation-fpga-ip-core\/","title":{"rendered":"Achieving beyond 7GB\/s transfer speeds on NVMe Gen4 SSD with next generation FPGA IP Core"},"content":{"rendered":"\n
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Welcome to our video in the Storage IP series. Today, we will showcase the powerful functionality of NVMeG4 IP core on the AMD Xilinx evaluation board. <\/p>\n\n\n\n

Our solution breaks barriers by enabling intermediate-grade FPGAs that lack PCIe Gen4 Hard IP, featuring only PCIe Gen3 Hard IPs or transceivers, to access NVMe Gen4 SSD. <\/p>\n\n\n\n

With the NVMeG4 IP, you can achieve data transfer at speed of 7400 Mbytes\/sec, doubling the speed compared to NVMe Gen3 SSDs. <\/p>\n\n\n\n

This means you can achieve exceptional throughput even on cost-effective FPGA models. <\/p>\n\n\n\n

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Design Gateway offers two types of NVMe IP cores: the NVMe IP using the PCIe Hard IP and the NVMe IP including the PCIe Soft IP. <\/p>\n\n\n\n

Compare the concepts behind these two types<\/h3>\n\n\n\n
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First, let’s take a brief look at the NVMe IP using the Hard IP. <\/p>\n\n\n\n

In this configuration, the NVMe Gen4 SSD is connected to the PCIe Gen4 Hard IP, which incorporates an FPGA transceiver for high-speed data transfer. <\/p>\n\n\n\n

The NVMe IP core facilitates direct connectivity between the SSD and the Hard IP, enabling the NVMe host function.<\/p>\n\n\n\n

To initiate data transfer with the SSD, the User Logic can simply generate Write or Read command requests. <\/p>\n\n\n\n

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Moving on to the second type of our NVMe IP core, it is designed for FPGAs that lack the PCIe Hard IP. <\/p>\n\n\n\n

In this scenario, only the transceiver is available for connecting with the SSD. <\/p>\n\n\n\n

To operate the PCIe Hard IP function, the PCIe Soft IP becomes necessary for interfacing with the transceiver. We refer to this configuration as the NVMeG4 IP, which includes the built-in PCIe Soft IP. <\/p>\n\n\n\n

Despite not utilizing the PCIe Gen4 Hard IP, it still provides the NVMe host function.<\/p>\n\n\n\n

Example comparing the FPGA models when using NVMeG4 IP and NVMe IP<\/h3>\n\n\n\n
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In this example, we’ll be focusing on the Kintex UltraScale+ model, the AMD Xilinx FPGA. <\/p>\n\n\n\n

From the provided table, we can observe that the smallest device model, KU3P, is capable of integrating the NVMeG4 IP. The unit price for this device is approximately 2,000 USD. <\/p>\n\n\n\n

On the other hand, using the NVMe IP requires a device that includes the PCIe Hard IP, the KU19P, which comes with a unit price of around 10,000 USD. Using the NVMeG4 IP can save significantly on the device cost. <\/p>\n\n\n\n

However, the resource utilization of the NVMeG4 IP, in comparison to the NVMe IP, is considerably larger due to the implementation of the PCIe Soft IP. <\/p>\n\n\n\n

Therefore, it depends on the users to determine which IP option best aligns with their system specifications.<\/p>\n\n\n\n

Board Setup<\/h3>\n\n\n\n
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To prepare the hardware for running the NVMeG4 IP demo, we will need the following components. <\/p>\n\n\n\n