{"id":2404,"date":"2025-05-07T19:30:00","date_gmt":"2025-05-07T12:30:00","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=2404"},"modified":"2025-08-25T09:30:27","modified_gmt":"2025-08-25T02:30:27","slug":"unboxing-the-1-nvme-ip-core-from-design-gateway","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2025\/05\/07\/unboxing-the-1-nvme-ip-core-from-design-gateway\/","title":{"rendered":"Unboxing the #1 FPGA Based NVMe IP core from Design Gateway"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">In the era of AI, real-time data processing, and edge computing, <strong>high-speed storage access<\/strong> is no longer optional\u2014it&#8217;s essential. That\u2019s why we\u2019re excited to introduce the <strong>NVMe-IP core<\/strong> from <a href=\"https:\/\/design-gateway.com\/\"><strong>Design Gateway<\/strong><\/a>\u2014a solution engineered for <strong>FPGA platforms<\/strong> that demand <strong>performance, reliability, and simplicity.<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83c\udfa5 <strong><a href=\"https:\/\/youtu.be\/LvcgAfGTzVY\" data-type=\"link\" data-id=\"https:\/\/youtu.be\/LvcgAfGTzVY\" target=\"_blank\" rel=\"noreferrer noopener\">Watch the Unboxing Video on YouTube<\/a><\/strong><\/p>\n\n\n\n<h3 class=\"wp-block-heading\">\u26a1 What Makes NVMe-IP Core #1?<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The <strong>NVMe-IP Core<\/strong> is more than just an IP block\u2014it&#8217;s a <strong>ready-to-integrate FPGA storage solution<\/strong> that eliminates the need for NVMe protocol expertise. It\u2019s designed for engineers who want to <strong>skip months of integration effort<\/strong> and <strong>go straight to performance<\/strong>.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Plug-and-play reference design<\/strong><\/li>\n\n\n\n<li><strong>Write speeds up to 3100 MB\/s<\/strong> (Agilex 5 demo)<\/li>\n\n\n\n<li><strong>Supports Altera &amp; AMD\/Xilinx FPGAs<\/strong><\/li>\n\n\n\n<li><strong>No CPU, no external DDR memory needed<\/strong><\/li>\n\n\n\n<li><strong>7 built-in commands<\/strong> including Write, Read, SMART, Secure Erase, and Flush<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83d\udd0d Why NVMe-IP from Design Gateway?<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>No NVMe Protocol Knowledge Required<\/strong> The IP comes with an out-of-the-box reference design, so you can integrate it <strong>without spending time learning the NVMe protocol stack<\/strong>.<\/li>\n\n\n\n<li><strong>Performance that Speaks Volumes<\/strong> Tested on the latest <strong>Sulfur Agilex 5 FPGA<\/strong>, our demo achieves <strong>3100 MB\/s write speed<\/strong>, outperforming previous platforms by a significant margin.<\/li>\n\n\n\n<li><strong>Professional Documentation<\/strong> From VHDL module breakdowns and firmware explanations to real signal timing diagrams\u2014you\u2019ll have everything you need to <strong>develop, customize, and deploy<\/strong> with confidence.<\/li>\n\n\n\n<li><strong>Broad Hardware Support<\/strong> Compatible with major Altera FPGAs like Agilex, Arria, Stratix, and Cyclone series, and tested with AB18, AB19, and AB20 PCIe adapter boards.<\/li>\n\n\n\n<li><strong>Free Evaluation Available<\/strong> Yes\u2014you can try the IP for free! Download the SOF file and test it on your own FPGA board before you buy.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83d\udce6 What\u2019s Inside the NVMe-IP Package?<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The IP core package includes:<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705 Pre-built <strong>Quartus\/Vivado projects<\/strong><br>\u2705 <strong>HDL modules<\/strong> with detailed documentation<br>\u2705 <strong>Embedded firmware<\/strong> with full source code<br>\u2705 <strong>SOF files<\/strong> for fast prototyping<br>\u2705 Evaluation-ready setup\u2014<strong>test before you buy!<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Whether you\u2019re working on <strong>defense-grade systems, high-speed imaging, AI inference, or financial trading platforms<\/strong>, NVMe-IP ensures <strong>deterministic latency and real-time throughput<\/strong>.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83e\uddea See It in Action<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">In our latest demo, we tested the NVMe-IP on the <strong>Altera Sulfur Agilex 5 FPGA<\/strong> using the <a href=\"https:\/\/www.mouser.com\/ProductDetail\/Design-Gateway\/AB19-M2PCI?qs=ulEaXIWI0c%2FRpgq%2FK19YQQ%3D%3D\" target=\"_blank\" rel=\"noreferrer noopener\"><strong>AB19 M.2-PCIe adapter board<\/strong><\/a> and achieved a blazing <strong>3100 MB\/s<\/strong> write speed\u2014<strong>a noticeable boost over previous generations<\/strong>.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udd17 <strong>Download the Evaluation SOF file for Free<\/strong>: <a href=\"https:\/\/dgway.com\/download\/download_form.html?d=NVMeIPTest_Config_SulfurAG5.zip\">https:\/\/dgway.com\/download\/download_form.html?d=NVMeIPTest_Config_SulfurAG5.zip<\/a><\/p>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83d\udccc Perfect for:<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705 FPGA Engineers<br>\u2705 Embedded Developers<br>\u2705 Industrial System Designers<br>\u2705 AI &amp; Robotics Innovators<br>\u2705 Data Acquisition Experts<br>\u2705 Research Institutions<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83d\udcec Ready to explore?<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udce5 Contact our team at <a href=\"https:\/\/dgway.com\/contact.html\">https:\/\/dgway.com\/contact.html<\/a><br>\ud83c\udf10 Visit the product page: <a href=\"https:\/\/dgway.com\/NVMe-IP_A_E.html\">https:\/\/dgway.com\/NVMe-IP_A_E.html<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udee0\ufe0f Want to try it yourself? <strong>Download the free SOF file<\/strong>, test it on your FPGA, and experience <strong>true high-performance NVMe storage<\/strong>.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">If you&#8217;re passionate about <strong>next-generation FPGA storage<\/strong>, <strong>low-latency systems<\/strong>, or building <strong>high-performance hardware<\/strong>, <strong>follow us<\/strong> for more IP releases, demos, and customer stories.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udd01 <strong>Like<\/strong>, \ud83d\udcac <strong>Comment<\/strong>, and \ud83d\udd17 <strong>Share<\/strong> this with your team or anyone exploring <strong>NVMe solutions on FPGA<\/strong>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>In the era of AI, real-time data processing, and edge computing, high-speed storage access is no longer optional\u2014it&#8217;s essential. That\u2019s why we\u2019re excited to introduce the NVMe-IP core from Design Gateway\u2014a solution engineered for FPGA platforms that demand performance, reliability, and simplicity. \ud83c\udfa5 Watch the Unboxing Video on YouTube \u26a1 What Makes NVMe-IP Core #1? The NVMe-IP Core is more&#46;&#46;&#46;<\/p>\n","protected":false},"author":1,"featured_media":2428,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[418,415,431,414,433,363,411,426,421,412,432,420,424,423,417,410,430,428,413,425,422,419,429,427],"class_list":["post-2404","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-storage","tag-ab19-m-2-pcie-adapter","tag-agilex-5-nvme-demo","tag-data-logging-with-nvme","tag-design-gateway-ip-core","tag-engineering-grade-ip-solutions","tag-fpga-hardware-acceleration","tag-fpga-storage-solution","tag-fpga-based-ssd-interface","tag-high-performance-embedded-design","tag-high-speed-ssd-on-fpga","tag-ip-core-unboxing-video","tag-low-latency-storage-solution","tag-nvme-ip-evaluation","tag-nvme-ip-for-engineers","tag-nvme-protocol-for-fpga","tag-nvme-ip-core-2","tag-nvme-ip-for-industrial-systems","tag-pcie-gen3-fpga-ip","tag-pcie-nvme-ip-core","tag-plug-and-play-nvme-ip","tag-quartus-reference-design","tag-real-time-data-acquisition","tag-ssd-interface-ip-for-fpga","tag-vhdl-ip-core"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2404","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=2404"}],"version-history":[{"count":4,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2404\/revisions"}],"predecessor-version":[{"id":2592,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2404\/revisions\/2592"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/2428"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=2404"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=2404"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=2404"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}