{"id":2646,"date":"2025-09-17T17:07:32","date_gmt":"2025-09-17T10:07:32","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=2646"},"modified":"2025-09-18T09:42:03","modified_gmt":"2025-09-18T02:42:03","slug":"design-gateway-x-dynanic-fpga-ip-collaboration-for-ultra-low-latency-hft","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2025\/09\/17\/design-gateway-x-dynanic-fpga-ip-collaboration-for-ultra-low-latency-hft\/","title":{"rendered":"Design Gateway \u00d7 DYNANIC: FPGA IP Collaboration for Ultra-Low-Latency HFT"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\"><strong>If you trade on microseconds, \u201cgood enough\u201d is a liability.<\/strong> You need ruthlessly fast, predictable, and easily upgradable tech. That\u2019s why <strong>Design Gateway<\/strong> and <strong>DYNANIC<\/strong> teamed up: pairing <strong>DG LL10G EMAC IP<\/strong> with <strong>Calypte\u2122 DMA IP<\/strong> to deliver <em>HFT-grade<\/em> latency while keeping your pricing engine agile. \ud83e\udde0\ud83d\udca1<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u25b6\ufe0f <strong>See it in action:<\/strong> Watch our short <strong>AAT-Calypte<\/strong> demo (full tick-to-trade loop + live RTT).<br><strong>YouTube:<\/strong> <a href=\"https:\/\/youtu.be\/RRpakEnK4lE\" target=\"_blank\" rel=\"noreferrer noopener\">FPGA IP Collaboration for Ultra-Low Latency High-Frequency Trading<\/a><\/p>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"Design Gateway \u00d7 Dynanic: FPGA IP Collaboration for Ultra-Low Latency High-Frequency Trading\" width=\"680\" height=\"383\" src=\"https:\/\/www.youtube.com\/embed\/RRpakEnK4lE?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83e\udded Two architectures traders actually use<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">1) Pricing Engine <strong>on card<\/strong> (all-FPGA) <\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>LL10G EMAC + market-data pipeline + pricing engine all on FPGA<\/li>\n\n\n\n<li><strong>Sub-microsecond<\/strong> latency &amp; deterministic behavior <\/li>\n\n\n\n<li>Best for compact, stable strategies <\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">2) Pricing Engine <strong>on software<\/strong> (hybrid) <\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">When models grow complex or strategies change frequently, moving pricing to software restores agility\u2014<strong>if<\/strong> the DMA bridge is ultra-low-latency.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>AAT-QDMA (Ubuntu):<\/strong> AMD QDMA\u2014free, full-featured, low latency <\/li>\n\n\n\n<li><strong>AAT-Calypte (RHEL):<\/strong> <strong>DYNANIC Calypte DMA<\/strong>\u2014<em>lower<\/em> latency &amp; <em>lighter<\/em> FPGA footprint <\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83c\udf1f Why Calypte wins for HFT-grade hybrid design<\/h2>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA-1024x576.jpg\" alt=\"Comparison graphic showing round-trip time latency for high-frequency trading on AMD Alveo X3522: the top setup (Design Gateway LL10G EMAC IP + DYNANIC Calypte DMA IP) measures ~4 microseconds, while the lower setup (LL10G EMAC IP + AMD QDMA IP) measures ~6 microseconds. A starburst badge reads \u201cAAT Calypte 33% faster,\u201d with a trading-chart background emphasizing ultra-low-latency FPGA performance.\" class=\"wp-image-2651\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA-1024x576.jpg 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA-300x169.jpg 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA-768x432.jpg 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA-1536x864.jpg 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/Calypte-DMA-vs-QDMA.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Calypte DMA vs. QDMA \u2014 33% Faster Round-Trip Latency for HFT (\u22484 \u03bcs vs 6 \u03bcs) on AMD Alveo X3522 with DG LL10GEMAC IP<\/figcaption><\/figure>\n<\/div>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Lower RTT:<\/strong> ~<strong>4 \u03bcs<\/strong> vs ~<strong>6 \u03bcs<\/strong> with QDMA (\u2248 <strong>33% faster<\/strong>)<\/li>\n\n\n\n<li><strong>Frees FPGA resources:<\/strong> ~<strong>30%<\/strong> of QDMA\u2019s footprint\u2014more room for book building, filters, and risk <\/li>\n\n\n\n<li><strong>Operationally simple on RHEL:<\/strong> Focused feature set tuned for trading workloads<\/li>\n<\/ul>\n\n\n\n<blockquote class=\"wp-block-quote is-layout-flow wp-block-quote-is-layout-flow\">\n<p class=\"wp-block-paragraph\">\ud83d\udcca <em>Lab results; performance varies by card, NIC\/FPGA, and workload.<\/em> <\/p>\n<\/blockquote>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83d\uddfa\ufe0f How the architecture works<\/h2>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits-1024x576.jpg\" alt=\"FPGA-only architecture showing LL10G EMAC IP, market-data processing, and an on-card pricing engine, alongside callouts listing constraints: complex trading algorithms, heavy ML\/statistical models, and frequently updated strategies that stress FPGA resources and deployment agility.\" class=\"wp-image-2650\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits-1024x576.jpg 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits-300x169.jpg 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits-768x432.jpg 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits-1536x864.jpg 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/on-card-limits.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">Limits of All-FPGA Pricing Engines in High-Frequency Trading<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\"><strong>On-card pricing:<\/strong> Ultimate determinism &amp; minimal latency, but can hit limits with <strong>complex algos<\/strong>, <strong>heavy ML\/stat models<\/strong>, or <strong>frequent updates<\/strong>.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram-1024x576.jpg\" alt=\"Hybrid HFT block diagram with host-side pricing engine on Ubuntu; FPGA integrates Design Gateway LL10G EMAC IP and a market-data processing engine; AMD QDMA IP acts as the DMA bridge transferring market data, orders, and control traffic between FPGA and software.\" class=\"wp-image-2649\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram-1024x576.jpg 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram-300x169.jpg 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram-768x432.jpg 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram-1536x864.jpg 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/qdma-diagram.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">AAT-QDMA Hybrid Architecture \u2013 AMD QDMA Baseline for HFT<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\"><strong>AAT-QDMA (software pricing on Ubuntu):<\/strong> AMD QDMA on Ubuntu is a solid, full-featured baseline. But HFT often demands even less latency and a smaller fabric footprint \u2014 the gap Calypte closes.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram-1024x576.jpg\" alt=\"Block diagram of the AAT-Calypte hybrid HFT platform: host software runs the pricing engine on Red Hat Enterprise Linux; FPGA card contains Design Gateway LL10G EMAC IP and a market-data processing engine; DYNANIC Calypte DMA IP provides bidirectional, ultra-low-latency data movement between FPGA and software.\" class=\"wp-image-2648\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram-1024x576.jpg 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram-300x169.jpg 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram-768x432.jpg 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram-1536x864.jpg 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2025\/09\/calypte-diagram.jpg 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\">AAT-Calypte Architecture \u2013 Ultra-Low-Latency FPGA\u2013Software Bridge for HFT<\/figcaption><\/figure>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\"><strong>AAT-Calypte (software pricing on RHEL):<\/strong> Host runs the <strong>Pricing Engine<\/strong>. On FPGA, <strong>DG LL10G EMAC IP<\/strong> ingests ticks, the <strong>market-data engine<\/strong> normalizes\/book-builds, and <strong>Calypte DMA IP<\/strong> bridges ticks\/orders\/control at ultra-low latency.<\/p>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83e\uddfe Comparison: Pricing Engine on Card vs. Software (QDMA &amp; Calypte)<\/h2>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th>Category<\/th><th>Pricing on Card (FPGA)<\/th><th>Software + QDMA (Ubuntu)<\/th><th>Software + Calypte (RHEL)<\/th><\/tr><\/thead><tbody><tr><td><strong>Best when<\/strong><\/td><td>Deterministic logic; small to mid\u2011size strategies; strictest latency budgets<\/td><td>Frequent updates; complex strategies<\/td><td><strong>Frequent updates; complex\/ML strategies with strict latency targets<\/strong><\/td><\/tr><tr><td><strong>Round-trip latency<\/strong> <strong>(Our Test)<\/strong><\/td><td><strong>Sub-\u03bcs<\/strong> <\/td><td>~<strong>6 \u03bcs<\/strong><\/td><td><strong>~4 \u03bcs<\/strong> (\u224833% faster vs. QDMA)<\/td><\/tr><tr><td><strong>DMA engine<\/strong><\/td><td>\u2014<\/td><td><strong>AMD QDMA<\/strong> (free, full-featured)<\/td><td><strong>DYNANIC Calypte<\/strong> (lightweight, ultra\u2011low\u2011latency)<\/td><\/tr><tr><td><strong>OS path<\/strong><\/td><td>FPGA only<\/td><td>Ubuntu userspace\/driver<\/td><td><strong>RHEL userspace\/driver<\/strong><\/td><\/tr><tr><td><strong>FPGA resources<\/strong><\/td><td>Consumed by pricing logic<\/td><td>Moderate DMA footprint <\/td><td><strong>Lower DMA footprint to free fabric<\/strong><\/td><\/tr><tr><td><strong>Update agility<\/strong><\/td><td>Low (HDL rebuild) <\/td><td>High (software deploy) <\/td><td><strong>High (software deploy)<\/strong> <\/td><\/tr><tr><td><strong>Typical use<\/strong><\/td><td>On\u2011card trading pipelines with DG LL10G EMAC<\/td><td>Hybrid HFT with AMD QDMA<\/td><td><strong>Hybrid HFT optimized for minimum latency<\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\ud83c\udfaf Who should consider Calypte first?<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Market-making, stat-arb, options MM<\/strong> desks needing constant iteration<\/li>\n\n\n\n<li><strong>Software-only teams<\/strong> seeking a step-change in latency without losing dev velocity <\/li>\n\n\n\n<li><strong>FPGA-constrained pipelines<\/strong> that still demand microseconds<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\">\u2705 Ready to build your perfected HFT platform?<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>\ud83d\udd36 <a href=\"https:\/\/dgway.com\/contact.html\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/contact.html\" target=\"_blank\" rel=\"noreferrer noopener\">Contact us today<\/a><\/strong> for combine DG LL10G EMAC IP, our AAT market-data pipeline, and DYNANIC Calypte DMA to accelerate time-to-alpha\u2014without sacrificing microsecond. \ud83d\udcc8<\/p>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h3 class=\"wp-block-heading\">\u2705 Get Started with Free Evaluation<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Download a <strong>Free Evaluation File<\/strong> and explore our FPGA IP in your own environment.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Free Evaluation <a href=\"https:\/\/dgway.com\/download\/download_form.html?d=LL10GEMACTest_ZCU102.zip\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/download\/download_form.html?d=LL10GEMACTest_ZCU102.zip\">LL10GEMAC-IP (AMD)<\/a> | <a href=\"https:\/\/dgway.com\/download\/download_form.html?d=LL10GEMACLpTest_Config_A10GX.zip\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/download\/download_form.html?d=LL10GEMACLpTest_Config_A10GX.zip\" target=\"_blank\" rel=\"noreferrer noopener\">LL10GEMAC-IP (Altera)<\/a><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h3 class=\"wp-block-heading\">\ud83c\udf10 Learn More<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>\ud83d\udccc<\/strong> <strong>Product Page:<\/strong> <a href=\"https:\/\/dgway.com\/Lowlatency-IP_X_E.html\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/Lowlatency-IP_X_E.html\" target=\"_blank\" rel=\"noreferrer noopener\">LL10GEMAC IP (AMD)<\/a> | <a href=\"https:\/\/dgway.com\/Lowlatency-IP_A_E.html\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/Lowlatency-IP_A_E.html\" target=\"_blank\" rel=\"noreferrer noopener\">LL10GEMAC IP (Altera)<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udcda <strong>Technical documents:<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udcc4 <strong>Documents for AMD<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>LL10GEMAC <a href=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_data_sheet_xilinx_en\/\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_data_sheet_xilinx_en\/\" target=\"_blank\" rel=\"noreferrer noopener\">Datasheet<\/a> | <a href=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_refdesign_xilinx_en\/\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_refdesign_xilinx_en\/\" target=\"_blank\" rel=\"noreferrer noopener\">Reference Design<\/a><\/li>\n\n\n\n<li>AAT Calypte DMA Instruction<\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udcc4 <strong>Documents for Altera<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>LL10GEMAC <a href=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_data_sheet_intel\/\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_data_sheet_intel\/\" target=\"_blank\" rel=\"noreferrer noopener\">Datasheet<\/a> | <a href=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_refdesign_intel\/\" data-type=\"link\" data-id=\"https:\/\/dgway.com\/products\/IP\/Lowlatency-IP\/dg_ll10gemacip_refdesign_intel\/\" target=\"_blank\" rel=\"noreferrer noopener\">Reference Design<\/a><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705 The <strong>LL10GEMAC IP Core<\/strong> is now available via official Partner Solution platforms.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/www.amd.com\/en\/search\/partner\/embedded-partner-solutions.html#\/7536\" data-type=\"link\" data-id=\"https:\/\/www.amd.com\/en\/search\/partner\/embedded-partner-solutions.html#\/7536\" target=\"_blank\" rel=\"noreferrer noopener\">AMD Adaptive Computing Partner Program<\/a> <\/li>\n\n\n\n<li><a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/partner\/showcase\/storefront\/a5S3b00000052D0EAI\/design-gateway.html\" data-type=\"link\" data-id=\"https:\/\/www.intel.com\/content\/www\/us\/en\/partner\/showcase\/storefront\/a5S3b00000052D0EAI\/design-gateway.html\" target=\"_blank\" rel=\"noreferrer noopener\">Intel \/ Altera FPGA Partner Solutions<\/a> <\/li>\n\n\n\n<li><a href=\"https:\/\/dyna-nic.com\/dma-solutions\/\" data-type=\"link\" data-id=\"https:\/\/dyna-nic.com\/dma-solutions\/\" target=\"_blank\" rel=\"noreferrer noopener\">DYNANIC DMA Solutions<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>If you trade on microseconds, \u201cgood enough\u201d is a liability. You need ruthlessly fast, predictable, and easily upgradable tech. That\u2019s why Design Gateway and DYNANIC teamed up: pairing DG LL10G EMAC IP with Calypte\u2122 DMA IP to deliver HFT-grade latency while keeping your pricing engine agile. \ud83e\udde0\ud83d\udca1 \u25b6\ufe0f See it in action: Watch our short AAT-Calypte demo (full tick-to-trade loop&#46;&#46;&#46;<\/p>\n","protected":false},"author":1,"featured_media":2654,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[4],"tags":[753,768,749,756,746,745,758,127,760,766,744,748,764,738,765,772,770,183,739,747,769,750,761,743,741,751,752,757,763,754,759,767,762,190,742,771,755,737],"class_list":["post-2646","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-low-latency","tag-10g-ethernet-mac","tag-33-faster-rtt","tag-aat-calypte","tag-amd-alveo-x3522","tag-amd-qdma","tag-calypte-dma-ip","tag-cesnet-ndk","tag-design-gateway","tag-deterministic-latency","tag-dma-benchmark","tag-dma-ip","tag-dynanic","tag-fintech-hardware-acceleration","tag-fpga-for-trading","tag-fpga-networking-ip","tag-fpga-software-co-design","tag-hft-infrastructure","tag-high-frequency-trading","tag-hybrid-hft-architecture","tag-ll10g-emac-ip","tag-low-jitter-ethernet","tag-market-data-engine","tag-market-making-technology","tag-microsecond-trading","tag-on-card-pricing-engine","tag-order-book","tag-order-entry-fix","tag-pcie-dma","tag-quant-trading-systems","tag-red-hat-enterprise-linux-rhel","tag-resource-efficient-fpga","tag-round-trip-latency","tag-statistical-arbitrage","tag-sub-microsecond-latency","tag-tick-to-trade-latency","tag-trading-system-architecture","tag-ubuntu-trading-stack","tag-ultra-low-latency-hft"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2646","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=2646"}],"version-history":[{"count":11,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2646\/revisions"}],"predecessor-version":[{"id":2663,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/2646\/revisions\/2663"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/2654"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=2646"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=2646"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=2646"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}