{"id":338,"date":"2022-03-29T19:59:16","date_gmt":"2022-03-29T12:59:16","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=338"},"modified":"2022-03-30T12:58:13","modified_gmt":"2022-03-30T05:58:13","slug":"001-mix-c-and-rtl-kernel","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2022\/03\/29\/001-mix-c-and-rtl-kernel\/","title":{"rendered":"#001 &#8211; Mix C++ and RTL kernel"},"content":{"rendered":"\n<h2 class=\"has-large-font-size wp-block-heading\"><strong>For Turnkey Accelerator System (TKAS-D2101) with Alveo U250 Card and Xilinx Vitis\u2122 Unified Software Platform 2021.1<\/strong><\/h2>\n\n\n\n<p>Based on Xilinx&#8217;s Vitis\u2122 Application Acceleration Development Flow Tutorials: <a href=\"https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/2021.2\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\">Mixing C++ and RTL Kernels<\/a><\/p>\n\n\n\n<p>This tutorial is split into two parts:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>In the first part, you will build an application (host and kernel) with one C++ based kernel. The host code, including the kernel function call, is reviewed.<br><\/li><li>In the second part, an RTL-based kernel will be added to the application. The updated host code, including the function call to the additional kernel, is reviewed.<\/li><\/ul>\n\n\n\n<p>During both parts, the application is built using a Makefile. Software emulation is run in step one and hardware emulation is run in step two. In both steps, the generated Application Timeline will be reviewed to highlight the kernels being called and run by the host application. The host code and C++ kernel code are supplied. The RTL code will be generated using the RTL Kernel Wizard.<\/p>\n\n\n\n<h1 class=\"has-large-font-size wp-block-heading\">Step by Step to run on TKAS-D2101<\/h1>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Set enviroment<\/h1>\n\n\n\n<p><code>source \/tools\/Xilinx\/Vitis\/2021.1\/settings64.sh<br>source \/opt\/xilinx\/xrt\/setup.sh<\/code><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Create working folder<\/h1>\n\n\n\n<p><code>mkdir alveo_example<\/code><br><code>cd alveo_example<\/code><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Clone from Github<\/h1>\n\n\n\n<p><code>git clone <a href=\"https:\/\/github.com\/Xilinx\/Vitis-Tutorials.git\">https:\/\/github.com\/Xilinx\/Vitis-Tutorials.git<\/a><\/code><br><code>cd Vitis-Tutorials<\/code><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples$ <mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\">git clone https:\/\/github.com\/Xilinx\/Vitis-Tutorials.git<\/mark>\nCloning into 'Vitis-Tutorials'...\nremote: Enumerating objects: 29932, done.\nremote: Counting objects: 100% (2168\/2168), done.\nremote: Compressing objects: 100% (1228\/1228), done.\nremote: Total 29932 (delta 940), reused 1581 (delta 666), pack-reused 27764\nReceiving objects: 100% (29932\/29932), 415.13 MiB | 5.25 MiB\/s, done.\nResolving deltas: 100% (15360\/15360), done.\nUpdating files: 100% (4088\/4088), done.\ntkas-user@tkas-d2101:~\/alveo_examples$ <mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\">cd Vitis-Tutorials<\/mark><\/code><\/pre>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Change git branch to 2021.1 to match with Vitis version 2021.1 on Turnkey Accelerator Systems<\/h1>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials$ <em><strong><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\">git status<\/mark><\/strong><\/em>\nOn branch 2021.2\nYour branch is up to date with 'origin\/2021.2'.\n\nnothing to commit, working tree clean\ntkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials$ <em><strong><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\">git checkout 2021.1<\/mark><\/strong><\/em>\nBranch '2021.1' set up to track remote branch '2021.1' from 'origin'.\nSwitched to a new branch '2021.1'\ntkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials$ <strong><em><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\">git log<\/mark><\/em><\/strong>\ncommit c84a09e50fdbbf7d1752740bea39218b2b639788 (HEAD -&gt; 2021.1, origin\/2021.1)\nAuthor: Ricky Su &lt;imrickysu@users.noreply.github.com&gt;\nDate:   Tue Mar 8 09:34:10 2022 +0800\n\n    PFM Kv260: update description for boot and sd_dir in step3 (#202)\n    \n    - preparing boot dir is to fulfill the Vitis IDE workflow requirements\n    - User don't need to add files to sd_dir directory\n\ncommit 65bccd541b96a1a865e34c6ac049433b2764666d\nAuthor: randyh62 &lt;42045079+randyh62@users.noreply.github.com&gt;\nDate:   Tue Jan 25 08:14:03 2022 -0800\n\n    HwAcc Intro: fix port name in connectivity ini to match wide_vadd.cpp (#177)\n    \n    * edited u200.ini to match wide_vadd.cpp\n    \n    * edited u250.ini to match wide_vadd.cpp\n\ncommit e902ab96065bbca73cf29933003d3fc9e73747da\nAuthor: Ricky Su &lt;imrickysu@users.noreply.github.com&gt;\nDate:   Wed Jan 19 23:14:15 2022 +0800\n\n    PFM VCK190: Apply 2021.2 enhancements to 2021.1\n    \n    Validation Makefile tests AIE test case\n    Add platforminfo Makefile\n    Step 3: explain more for boot components\n    Step 4: switch the order of hw-emu and hw build. Usually we do hw-emu before hw.\n    Step 4: fix sysroot path to cortexa72-cortexa53-xilinx-linux for PetaLinux 2021.1 update\ntkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials$<\/code><\/pre>\n\n\n\n<h1 class=\"has-large-font-size wp-block-heading\">1st: Build &amp; Run C++ based kernel on <mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-cyan-blue-color\">run1 <\/mark>folder<\/h1>\n\n\n\n<p><code>cd Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1<\/code><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Change configuration for Alveo U250 Card<\/h1>\n\n\n\n<p><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\"><strong>File #1<\/strong> design.cfg : <br>Line 1 | platform=xilinx_u250_gen3x16_xdma_3_1_202020_1<br><br><strong>File #2<\/strong> Makefile : <br>Line 19 | DEVICE := xilinx_u250_gen3x16_xdma_3_1_202020_1<br>Line 25 | From &#8220;-lpthread&#8221; to &#8220;-pthread&#8221;<\/mark><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Build for software emulation<\/h1>\n\n\n\n<p><code>make all TARGET=sw_emu<\/code><\/p>\n\n\n\n<p>This builds both the host software and hardware binary targeted to software emulation. The makefile will also generate the platform JSON emulation file to use during emulation.<\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Make result<\/h1>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1$ make all TARGET=sw_emu\ng++ -I\/opt\/xilinx\/xrt\/include\/ -I\/tools\/Xilinx\/Vivado\/2021.1\/include\/ -Wall -O0 -g -std=c++11 -L\/opt\/xilinx\/xrt\/lib\/ -lOpenCL -lpthread -lrt -lstdc++ -o 'host' '..\/src\/host\/host_step1.cpp' -lOpenCL\nv++ -t sw_emu --config design.cfg -c -k krnl_vadd -I'..\/src\/kernel_cpp' -o'krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo' '..\/src\/kernel_cpp\/krnl_vadd.cpp'\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2021.1\/data\/vitis\/vpp\/optMap.xml'\n\n****** v++ v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ compile can be found at:\n\tReports: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/reports\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1\n\tLog files: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/logs\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1\nRunning Dispatch Server on port: 42635\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo.compile_summary, at Sat Mar 19 15:21:53 2022\nINFO: &#91;v++ 60-1316] Initiating connection to rulecheck server, at Sat Mar 19 15:21:53 2022\nRunning Rule Check Server on port:42461\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/reports\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1\/v++_compile_krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_guidance.html', at Sat Mar 19 15:21:54 2022\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/hw\/hw.xsa'\nINFO: &#91;v++ 74-78] Compiler Version string: 2021.1\nINFO: &#91;v++ 60-585] Compiling for software emulation target\nINFO: &#91;v++ 60-423]   Target device: xilinx_u250_gen3x16_xdma_3_1_202020_1\nINFO: &#91;v++ 60-242] Creating kernel: 'krnl_vadd'\nINFO: &#91;v++ 60-594] Finished kernel compilation\nINFO: &#91;v++ 60-586] Created krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. \n    vitis_analyzer \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo.compile_summary \nINFO: &#91;v++ 60-791] Total elapsed time: 0h 0m 17s\nINFO: &#91;v++ 60-1653] Closing dispatch client.\nv++ -t sw_emu --config design.cfg -l -o'krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin' krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2021.1\/data\/vitis\/vpp\/optMap.xml'\n\n****** v++ v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ link can be found at:\n\tReports: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/reports\/link\n\tLog files: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/logs\/link\nRunning Dispatch Server on port: 40165\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin.link_summary, at Sat Mar 19 15:22:12 2022\nINFO: &#91;v++ 60-1316] Initiating connection to rulecheck server, at Sat Mar 19 15:22:12 2022\nRunning Rule Check Server on port:41281\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/reports\/link\/v++_link_krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_guidance.html', at Sat Mar 19 15:22:13 2022\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/hw\/hw.xsa'\nINFO: &#91;v++ 74-78] Compiler Version string: 2021.1\nINFO: &#91;v++ 60-629] Linking for software emulation target\nINFO: &#91;v++ 60-423]   Target device: xilinx_u250_gen3x16_xdma_3_1_202020_1\nINFO: &#91;v++ 60-645] kernel flags are '-g -I \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/src\/kernel_cpp -g'\nWARNING: &#91;v++ 60-2336] Parameter compiler.enableSlrComputeUnitDrc was set to true, but no SLRs were specified via the command line.\nINFO: &#91;v++ 60-586] Created krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nINFO: &#91;v++ 60-1307] Run completed. Additional information can be found in:\n\tGuidance: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/reports\/link\/v++_link_krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_guidance.html\n\tSteps Log File: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/_x\/logs\/link\/link.steps.log\n\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. \n    vitis_analyzer \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1\/krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin.link_summary \nINFO: &#91;v++ 60-791] Total elapsed time: 0h 0m 15s\nINFO: &#91;v++ 60-1653] Closing dispatch client.\nemconfigutil --platform xilinx_u250_gen3x16_xdma_3_1_202020_1\n\n****** configutil v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;ConfigUtil 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm\nINFO: &#91;ConfigUtil 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/hw\/hw.xsa'\nINFO: &#91;ConfigUtil 60-1032]  \nemulation configuration file `emconfig.json` is created in current working directory \ntkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1$<\/code><\/pre>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Run software emulation<\/h1>\n\n\n\n<p>set emulation enviroment<\/p>\n\n\n\n<p><code>export XCL_EMULATION_MODE=sw_emu<\/code><\/p>\n\n\n\n<p>Run by the following command<\/p>\n\n\n\n<p><code>.\/host krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin<br><\/code><\/p>\n\n\n\n<p>Run result<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run1$ .\/host krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nUsing FPGA binary file specfied through the command line: krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nFound Platform\nPlatform Name: Xilinx\nLoading: 'krnl_vadd.sw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin'\nTEST WITH ONE KERNEL PASSED<\/code><\/pre>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"130\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image00-1024x130.png\" alt=\"\" class=\"wp-image-399\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image00-1024x130.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image00-300x38.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image00-768x98.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image00.png 1268w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p class=\"has-medium-font-size\"><strong>Review the Application Timeline<\/strong><\/p>\n\n\n\n<p>Review the Application Timeline generated during software emulation to visualize the host events and the kernel running.vitis_analyzer xclbin.run_summaryClick on the Application Timeline option on the left to bring up the Application Timeline.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"606\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image01-1024x606.png\" alt=\"\" class=\"wp-image-401\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image01-1024x606.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image01-300x178.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image01-768x455.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image01.png 1301w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<h1 class=\"has-large-font-size wp-block-heading\">2nd: Building an Application with C++ and RTL-Based Kernels<\/h1>\n\n\n\n<p>Create and package an RTL-based kernel using the RTL Kernel Wizard<\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Create the Vitis Project<\/h1>\n\n\n\n<p>Run vitis <\/p>\n\n\n\n<p><code>vitis<\/code><\/p>\n\n\n\n<p>Select <em><strong>.\/mixing-c-rtl-kernels\/workspace<\/strong><\/em> as the workspace directory, and click Launch.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"444\" height=\"217\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image02.png\" alt=\"\" class=\"wp-image-402\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image02.png 444w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image02-300x147.png 300w\" sizes=\"auto, (max-width: 444px) 100vw, 444px\" \/><figcaption>reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>From the Welcome screen select<em> <strong>Create Application Project<\/strong><\/em> to open the New Project wizard.<br>The first page displays a summary of the process. Click <strong><em>Next<\/em><\/strong> to proceed.<br>From the Platform page select the <em><strong>xilinx_u250_gen3x16_xdma_3_1_202020_1 platform<\/strong><\/em> and click <strong><em>Next<\/em><\/strong>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"848\" height=\"681\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image03.png\" alt=\"\" class=\"wp-image-403\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image03.png 848w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image03-300x241.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image03-768x617.png 768w\" sizes=\"auto, (max-width: 848px) 100vw, 848px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>From the <strong><em>Application Project Details<\/em><\/strong> page, name your project <strong><em>rtl_project<\/em><\/strong> and click <strong><em>Next<\/em><\/strong>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"858\" height=\"692\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image04.png\" alt=\"\" class=\"wp-image-404\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image04.png 858w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image04-300x242.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image04-768x619.png 768w\" sizes=\"auto, (max-width: 858px) 100vw, 858px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>Under<strong><em> SW Acceleration Templates<\/em><\/strong>, select <strong><em>Empty Application<\/em><\/strong>, and click <strong><em>Finish<\/em><\/strong>. <br>This creates a Vitis IDE project.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"552\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image05-1024x552.png\" alt=\"\" class=\"wp-image-405\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image05-1024x552.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image05-300x162.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image05-768x414.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image05.png 1394w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>Next, generate an RTL-based kernel from within the Vitis IDE.<br>Select the menu command <strong><em>Xilinx &gt; Launch RTL Kernel Wizard &gt; rtl_project_kernels<\/em><\/strong>. <br>This opens the <strong><em>RTL Kernel Wizard<\/em><\/strong> Welcome page.The first page is a summary of the process. <br>Review it and click <strong><em>Next<\/em><\/strong>. In the <strong><em>General Settings<\/em><\/strong> dialog box, keep all the default settings, and click <strong><em>Next<\/em><\/strong>.<br>In the <strong><em>Scalars<\/em><\/strong> dialog box, set the number of scalar arguments to 0, and click <strong><em>Next<\/em><\/strong>.<br>In the<strong><em> Global Memory<\/em><\/strong> dialog box, keep all the default settings, and click <strong><em>Next<\/em><\/strong>.<br>In the <strong><em>Streaming Interfaces<\/em><\/strong> dialog box, keep all the default settings, and click <em>Next<\/em>. <br><em>Note: This tutorial doesn&#8217;t have AXI steam interface<\/em><\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"591\" height=\"530\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image06.png\" alt=\"\" class=\"wp-image-406\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image06.png 591w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image06-300x269.png 300w\" sizes=\"auto, (max-width: 591px) 100vw, 591px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>The <strong><em>Summary <\/em><\/strong>dialog box is displayed and provides a summary of the RTL kernel settings and includes a function prototype which conveys what a kernel call would look like as a C function.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"744\" height=\"525\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image07.png\" alt=\"\" class=\"wp-image-407\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image07.png 744w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image07-300x212.png 300w\" sizes=\"auto, (max-width: 744px) 100vw, 744px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>Click <strong><em>OK<\/em><\/strong>. The RTL Kernel source files have now been created and Vivado opens a project automatically with the generated RTL code corresponding to the default A = A + 1 function.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"508\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08-1024x508.png\" alt=\"\" class=\"wp-image-408\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08-1024x508.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08-300x149.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08-768x381.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08-1536x762.png 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image08.png 1629w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>You can navigate to review the source files or even run RTL simulation. However, for this tutorial, you will not be modifying the default RTL Kernel and will only package into an object file (.xo).<\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Generate RTL Kernel<\/h1>\n\n\n\n<p>In <strong><em>Flow Navigator<\/em><\/strong>, click <em><strong>Generate RTL Kernel<\/strong><\/em>.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"794\" height=\"562\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image09.png\" alt=\"\" class=\"wp-image-409\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image09.png 794w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image09-300x212.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image09-768x544.png 768w\" sizes=\"auto, (max-width: 794px) 100vw, 794px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>In the <strong><em>Generate RTL Kernel<\/em><\/strong> dialog box, select the <strong><em>Sources-only packaging<\/em><\/strong> option.<br>For Software Emulation Sources, you can add a C++ model of the RTL kernel, <br>which is used for Software Emulation.<\/p>\n\n\n\n<blockquote class=\"wp-block-quote is-layout-flow wp-block-quote-is-layout-flow\"><p><br><em>The C++ model must be coded by the design engineer. Typically, there is no C++ model available, and Hardware Emulation is used to test the design. Because the RTL Wizard creates a C++ model of the vadd design, the steps to add this file are also provided below.<\/em><br><\/p><\/blockquote>\n\n\n\n<p>Click the <strong><em>Browse <\/em><\/strong>command (&#8230;). Double-click the imports directory.<br>Select the <strong><em>rtl_kernel_wizard_0_cmodel.cpp<\/em><\/strong> file and click <strong><em>OK<\/em><\/strong>.To generate the RTL kernel.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"856\" height=\"668\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image10.png\" alt=\"\" class=\"wp-image-410\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image10.png 856w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image10-300x234.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image10-768x599.png 768w\" sizes=\"auto, (max-width: 856px) 100vw, 856px\" \/><\/figure>\n\n\n\n<p>After the RTL kernel has been generated successfully, click <strong><em>Yes <\/em><\/strong><br>to exit the Vivado Design Suite, and return to the Vitis IDE.<br>A message window displays some information related to the generated RTL kernel. <br>Review it and click <strong><em>OK<\/em><\/strong>. <br>Exit the Vitis IDE.At this point, you have packaged the RTL kernel into the following object file, <strong><em>rtl_kernel_wizard_0.xo<\/em><\/strong> found in the following directory <\/p>\n\n\n\n<p><mark style=\"background-color:#abb8c3\" class=\"has-inline-color\">..\/02-mixing-c-rtl-kernels\/workspace\/rtl_project_kernels\/src\/vitis_rtl_kernel\/rtl_kernel_wizard_0\u00a0<\/mark><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"70\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image11-1024x70.png\" alt=\"\" class=\"wp-image-411\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image11-1024x70.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image11-300x20.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image11-768x52.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image11.png 1264w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Description of Host application source code<\/h1>\n\n\n\n<p>See detail in <br><a href=\"https:\/\/xilinx.github.io\/Vitis-Tutorials\/2021-1\/build\/html\/docs\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/README.html\">https:\/\/xilinx.github.io\/Vitis-Tutorials\/2021-1\/build\/html\/docs\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/README.html<\/a><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Build and Emulation with C++ and RTL Based Kernels<\/h1>\n\n\n\n<p>With the RTL-based kernel added and host code updated, build the application, targeting hardware emulation through the updated makefile in the run2 directory. The makefile has been updated to add both the CPP and RTL-based kernels to the hardware platform file (xclbin).<br>Navigate to the .\/02-mixing-c-rtl-kernels\/reference-files\/run2 directory.<br><strong>Change plaform in the following files to match with your Alveo Card (<\/strong>xilinx_u250_gen3x16_xdma_3_1_202020_1<strong>)<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>compile.cfg<\/li><li>link.cfg<\/li><li>and Makefile for Alveo U250 Card<\/li><\/ul>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Here are summary changed in Makefile<\/h1>\n\n\n\n<p><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-vivid-green-cyan-color\"><strong>Line 18 |<\/strong> DEVICE := xilinx_u250_gen3x16_xdma_3_1_202020_1<br><strong>Line 24 |<\/strong> CXXFLAGS := -I$(XILINX_XRT)\/include\/ -I$(XILINX_VIVADO)\/include\/ -Wall -O0 -g -std=c++11 -L$(XILINX_XRT)\/lib\/ -lOpenCL -pthread -lrt -lstdc++<br><strong>Line 30-32 | <\/strong><br>LDCLFLAGS += &#8211;profile.data=all:all:all<br>LDCLFLAGS += &#8211;profile.stall=all:all:all<br>LDCLFLAGS += &#8211;profile.exec=all:all:all<\/mark><\/p>\n\n\n\n<p>To build the application targeting hardware emulation, run the following makefile from the <br><strong><em>.\/reference-files\/run2<\/em><\/strong> directory.<\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Build result<\/h1>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2$ make all TARGET=hw_emu\ng++ -I\/opt\/xilinx\/xrt\/include\/ -I\/tools\/Xilinx\/Vivado\/2021.1\/include\/ -Wall -O0 -g -std=c++11 -L\/opt\/xilinx\/xrt\/lib\/ -lOpenCL -pthread -lrt -lstdc++ -o 'host' '..\/src\/host\/host_step2.cpp' -lOpenCL\nv++ -t hw_emu --config link.cfg --profile.data=all:all:all --profile.stall=all:all:all --profile.exec=all:all:all -l -o'krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin' krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo ..\/..\/script\/workplace\/rtl_project\/src\/rtl_kernel\/rtl_kernel_wizard_0\/rtl_kernel_wizard_0.xo\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2021.1\/data\/vitis\/vpp\/optMap.xml'\n\n****** v++ v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ link can be found at:\n\tReports: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/reports\/link\n\tLog files: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/logs\/link\nRunning Dispatch Server on port: 36021\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin.link_summary, at Sat Mar 19 16:53:17 2022\nINFO: &#91;v++ 60-1316] Initiating connection to rulecheck server, at Sat Mar 19 16:53:17 2022\nRunning Rule Check Server on port:42111\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/reports\/link\/v++_link_krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_guidance.html', at Sat Mar 19 16:53:18 2022\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/hw\/hw.xsa'\nINFO: &#91;v++ 74-78] Compiler Version string: 2021.1\nINFO: &#91;v++ 60-629] Linking for hardware emulation target\nINFO: &#91;v++ 60-423]   Target device: xilinx_u250_gen3x16_xdma_3_1_202020_1\nINFO: &#91;v++ 60-1332] Run 'run_link' status: Not started\nINFO: &#91;v++ 60-1443] &#91;16:53:20] Run run_link: Step system_link: Started\nINFO: &#91;v++ 60-1453] Command Line: system_link --xo \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo --xo \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/script\/workplace\/rtl_project\/src\/rtl_kernel\/rtl_kernel_wizard_0\/rtl_kernel_wizard_0.xo --config \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/syslinkConfig.ini --xpfm \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm --target emu --output_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int --temp_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sat Mar 19 16:53:21 2022\nINFO: &#91;SYSTEM_LINK 82-70] Extracting xo v3 file \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xo\nINFO: &#91;SYSTEM_LINK 82-70] Extracting xo v3 file \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/script\/workplace\/rtl_project\/src\/rtl_kernel\/rtl_kernel_wizard_0\/rtl_kernel_wizard_0.xo\nINFO: &#91;SYSTEM_LINK 82-53] Creating IP database \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:53:21] build_xd_ip_db started: \/tools\/Xilinx\/Vitis\/2021.1\/bin\/build_xd_ip_db -ip_search 0  -sds-pf \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/hw_emu\/pfm_dynamic_emu.hpfm -clkid 0 -ip \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/iprepo\/xilinx_com_hls_krnl_vadd_1_0,krnl_vadd -ip \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/iprepo\/mycompany_com_kernel_rtl_kernel_wizard_0_1_0,rtl_kernel_wizard_0 -o \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:53:24] build_xd_ip_db finished successfully\nTime (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2005.691 ; gain = 0.000 ; free physical = 16956 ; free virtual = 35412\nINFO: &#91;SYSTEM_LINK 82-51] Create system connectivity graph\nINFO: &#91;SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:53:24] cfgen started: \/tools\/Xilinx\/Vitis\/2021.1\/bin\/cfgen  -nk krnl_vadd:1:krnl_vadd_1 -nk rtl_kernel_wizard_0:1:rtl_kernel_wizard_0_1 -dmclkid 0 -r \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml -o \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml\nINFO: &#91;CFGEN 83-0] Kernel Specs: \nINFO: &#91;CFGEN 83-0]   kernel: krnl_vadd, num: 1  {krnl_vadd_1}\nINFO: &#91;CFGEN 83-0]   kernel: rtl_kernel_wizard_0, num: 1  {rtl_kernel_wizard_0_1}\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument krnl_vadd_1.a to DDR&#91;1]\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument krnl_vadd_1.b to DDR&#91;1]\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument krnl_vadd_1.c to DDR&#91;1]\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument rtl_kernel_wizard_0_1.axi00_ptr0 to DDR&#91;1]\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:53:28] cfgen finished successfully\nTime (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2005.691 ; gain = 0.000 ; free physical = 16954 ; free virtual = 35410\nINFO: &#91;SYSTEM_LINK 82-52] Create top-level block diagram\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:53:28] cf2bd started: \/tools\/Xilinx\/Vitis\/2021.1\/bin\/cf2bd  --linux --trace_buffer 1024 --input_file \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml --ip_db \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml --cf_name dr --working_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.xsd --temp_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link --output_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int --target_bd hw_emu\/pfm_dynamic\/pfm_dynamic.bd\nINFO: &#91;CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml -r \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml -o dr.xml\nINFO: &#91;CF2BD 82-28] cf2xd finished successfully\nINFO: &#91;CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd hw_emu\/pfm_dynamic\/pfm_dynamic.bd -dn dr -dp \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/sys_link\/_sysl\/.xsd\nINFO: &#91;CF2BD 82-28] cf_xsd finished successfully\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:53:31] cf2bd finished successfully\nTime (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2005.691 ; gain = 0.000 ; free physical = 16947 ; free virtual = 35410\nINFO: &#91;v++ 60-1441] &#91;16:53:31] Run run_link: Step system_link: Completed\nTime (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 16991 ; free virtual = 35449\nINFO: &#91;v++ 60-1443] &#91;16:53:31] Run run_link: Step cf2sw: Started\nINFO: &#91;v++ 60-1453] Command Line: cf2sw -sdsl \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/sdsl.dat -rtd \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/cf2sw.rtd -nofilter \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/cf2sw_full.rtd -xclbin \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/xclbin_orig.xml -o \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/xclbin_orig.1.xml\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;v++ 60-1441] &#91;16:53:34] Run run_link: Step cf2sw: Completed\nTime (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 16990 ; free virtual = 35450\nINFO: &#91;v++ 60-1443] &#91;16:53:34] Run run_link: Step rtd2_system_diagram: Started\nINFO: &#91;v++ 60-1453] Command Line: rtd2SystemDiagram\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;v++ 60-1441] &#91;16:53:34] Run run_link: Step rtd2_system_diagram: Completed\nTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 16982 ; free virtual = 35442\nINFO: &#91;v++ 60-1443] &#91;16:53:34] Run run_link: Step vpl: Started\nINFO: &#91;v++ 60-1453] Command Line: vpl -t hw_emu -f xilinx_u250_gen3x16_xdma_3_1_202020_1 -g --remote_ip_cache \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/.ipcache --output_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int --log_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/logs\/link --report_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/reports\/link --config \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/vplConfig.ini -k \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/kernel_info.dat --webtalk_flag Vitis --temp_dir \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link --emulation_mode debug_waveform --no-info --iprepo \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/xo\/ip_repo\/mycompany_com_kernel_rtl_kernel_wizard_0_1_0 --iprepo \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/xo\/ip_repo\/xilinx_com_hls_krnl_vadd_1_0 --messageDb \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\/vpl.pb \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/dr.bd.tcl\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\n\n****** vpl v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;VPL 60-839] Read in kernel information from file '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/kernel_info.dat'.\nINFO: &#91;VPL 74-78] Compiler Version string: 2021.1\nINFO: &#91;VPL 60-423]   Target device: xilinx_u250_gen3x16_xdma_3_1_202020_1\nINFO: &#91;VPL 60-1032] Extracting hardware platform to \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/vivado\/vpl\/.local\/hw_platform\n&#91;16:53:43] Run vpl: Step create_project: Started\nCreating Vivado project.\n&#91;16:53:43] Run vpl: Step create_project: Completed\n&#91;16:53:43] Run vpl: Step create_bd: Started\n&#91;16:53:51] Run vpl: Step create_bd: Completed\n&#91;16:53:51] Run vpl: Step update_bd: Started\n&#91;16:53:54] Run vpl: Step update_bd: Completed\n&#91;16:53:54] Run vpl: Step generate_target: Started\n&#91;16:55:09] Run vpl: Step generate_target: RUNNING...\n&#91;16:55:25] Run vpl: Step generate_target: Completed\n&#91;16:55:25] Run vpl: Step config_hw_emu.gen_scripts: Started\n&#91;16:55:38] Run vpl: Step config_hw_emu.gen_scripts: Completed\n&#91;16:55:38] Run vpl: Step config_hw_emu.compile: Started\n&#91;16:56:11] Run vpl: Step config_hw_emu.compile: Completed\n&#91;16:56:11] Run vpl: Step config_hw_emu.elaborate: Started\n&#91;16:56:31] Run vpl: Step config_hw_emu.elaborate: Completed\n&#91;16:56:32] Run vpl: FINISHED. Run Status: config_hw_emu.elaborate Complete!\nINFO: &#91;v++ 60-1441] &#91;16:56:32] Run run_link: Step vpl: Completed\nTime (s): cpu = 00:00:04 ; elapsed = 00:02:58 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 13727 ; free virtual = 33337\nINFO: &#91;v++ 60-1443] &#91;16:56:32] Run run_link: Step rtdgen: Started\nINFO: &#91;v++ 60-1453] Command Line: rtdgen\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;v++ 60-991] clock name 'kernel2_clk\/clk' (clock ID '1') is being mapped to clock name 'KERNEL_CLK' in the xclbin\nINFO: &#91;v++ 60-991] clock name 'kernel_clk\/clk' (clock ID '0') is being mapped to clock name 'DATA_CLK' in the xclbin\nINFO: &#91;v++ 60-1230] The compiler selected the following frequencies for the runtime controllable kernel clock(s) and scalable system clock(s): Kernel (KERNEL) clock: kernel2_clk\/clk = 500, Kernel (DATA) clock: kernel_clk\/clk = 300\nINFO: &#91;v++ 60-1453] Command Line: cf2sw -a \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/address_map.xml -sdsl \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/sdsl.dat -xclbin \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/xclbin_orig.xml -rtd \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.rtd -o \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xml\nINFO: &#91;v++ 60-1652] Cf2sw returned exit code: 0\nWARNING: &#91;v++ 60-1455] Debuggable symbols are not generated successfully, clean up \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/consolidated.cf\nINFO: &#91;v++ 60-1441] &#91;16:56:36] Run run_link: Step rtdgen: Completed\nTime (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 15710 ; free virtual = 35356\nINFO: &#91;v++ 60-1443] &#91;16:56:36] Run run_link: Step xclbinutil: Started\nINFO: &#91;v++ 60-1453] Command Line: xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/debug_ip_layout.rtd --add-section BITSTREAM:RAW:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/behav.xse --force --target hw_emu --key-value SYS:dfx_enable:false --add-section :JSON:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.rtd --append-section :JSON:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/appendSection.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_xml.rtd --add-section BUILD_METADATA:JSON:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_build.rtd --add-section EMBEDDED_METADATA:RAW:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xml --add-section SYSTEM_METADATA:RAW:\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_u250_gen3x16_xdma_3_1_202020_1 --output \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nXRT Build Version: 2.11.634 (2021.1)\n       Build Date: 2021-06-08 22:08:45\n          Hash ID: 5ad5998d67080f00bca5bf15b3838cf35e0a7b26\nCreating a default 'in-memory' xclbin image.\n\nSection: 'DEBUG_IP_LAYOUT'(9) was successfully added.\nSize   : 1160 bytes\nFormat : JSON\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/debug_ip_layout.rtd'\n\nSection: 'BITSTREAM'(0) was successfully added.\nSize   : 38507581 bytes\nFormat : RAW\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/behav.xse'\n\nSection: 'MEM_TOPOLOGY'(6) was successfully added.\nFormat : JSON\nFile   : 'mem_topology'\n\nSection: 'IP_LAYOUT'(8) was successfully added.\nFormat : JSON\nFile   : 'ip_layout'\n\nSection: 'CONNECTIVITY'(7) was successfully added.\nFormat : JSON\nFile   : 'connectivity'\n\nSection: 'CLOCK_FREQ_TOPOLOGY'(11) was successfully added.\nSize   : 274 bytes\nFormat : JSON\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_xml.rtd'\n\nSection: 'BUILD_METADATA'(14) was successfully added.\nSize   : 3069 bytes\nFormat : JSON\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_build.rtd'\n\nSection: 'EMBEDDED_METADATA'(2) was successfully added.\nSize   : 4665 bytes\nFormat : RAW\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xml'\n\nSection: 'SYSTEM_METADATA'(22) was successfully added.\nSize   : 9595 bytes\nFormat : RAW\nFile   : '\/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/int\/systemDiagramModelSlrBaseAddress.json'\n\nSection: 'PARTITION_METADATA'(20) was successfully appended to.\nFormat : JSON\nFile   : 'partition_metadata'\n\nSection: 'IP_LAYOUT'(8) was successfully appended to.\nFormat : JSON\nFile   : 'ip_layout'\nSuccessfully wrote (38544271 bytes) to the output file: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nLeaving xclbinutil.\nINFO: &#91;v++ 60-1441] &#91;16:56:36] Run run_link: Step xclbinutil: Completed\nTime (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 15672 ; free virtual = 35354\nINFO: &#91;v++ 60-1443] &#91;16:56:36] Run run_link: Step xclbinutilinfo: Started\nINFO: &#91;v++ 60-1453] Command Line: xclbinutil --quiet --force --info \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin.info --input \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;v++ 60-1441] &#91;16:56:37] Run run_link: Step xclbinutilinfo: Completed\nTime (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 15672 ; free virtual = 35354\nINFO: &#91;v++ 60-1443] &#91;16:56:37] Run run_link: Step generate_sc_driver: Started\nINFO: &#91;v++ 60-1453] Command Line: \nINFO: &#91;v++ 60-1454] Run Directory: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/link\/run_link\nINFO: &#91;v++ 60-1441] &#91;16:56:37] Run run_link: Step generate_sc_driver: Completed\nTime (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.484 ; gain = 0.000 ; free physical = 15672 ; free virtual = 35354\nWARNING: &#91;v++ 60-2336] Parameter compiler.enableSlrComputeUnitDrc was set to true, but no SLRs were specified via the command line.\nINFO: &#91;v++ 60-244] Generating system estimate report...\nINFO: &#91;v++ 60-1092] Generated system estimate report: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/reports\/link\/system_estimate_krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xtxt\nINFO: &#91;v++ 60-586] Created krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nINFO: &#91;v++ 60-1307] Run completed. Additional information can be found in:\n\tGuidance: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/reports\/link\/v++_link_krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1_guidance.html\n\tSteps Log File: \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/_x\/logs\/link\/link.steps.log\n\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. \n    vitis_analyzer \/home\/tkas-user\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2\/krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin.link_summary \nINFO: &#91;v++ 60-791] Total elapsed time: 0h 3m 30s\nINFO: &#91;v++ 60-1653] Closing dispatch client.\nemconfigutil --platform xilinx_u250_gen3x16_xdma_3_1_202020_1\n\n****** configutil v2021.1 (64-bit)\n  **** SW Build 3246112 on 2021-06-09-14:19:56\n    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.\n\nINFO: &#91;ConfigUtil 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/xilinx_u250_gen3x16_xdma_3_1_202020_1.xpfm\nINFO: &#91;ConfigUtil 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u250_gen3x16_xdma_3_1_202020_1\/hw\/hw.xsa'\nINFO: &#91;ConfigUtil 60-1032]  \nemulation configuration file `emconfig.json` is created in current working directory<\/code><\/pre>\n\n\n\n<p>As before, run emulation, and generate and review the Application Timeline by running the following commands from within the run2 directory.Set XCL_EMULATION_MODE environment variable for hardware emulation and Run hardware Emulation<\/p>\n\n\n\n<p><code>export XCL_EMULATION_MODE=hw_emu<br>.\/host krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin<\/code><\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">Output message from running hardware emulation<\/h1>\n\n\n\n<pre class=\"wp-block-code\"><code>tkas-user@tkas-d2101:~\/alveo_examples\/Vitis-Tutorials\/Hardware_Acceleration\/Feature_Tutorials\/02-mixing-c-rtl-kernels\/reference-files\/run2$ .\/host krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nUsing FPGA binary file specfied through the command line: krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin\nFound Platform\nPlatform Name: Xilinx\nLoading: 'krnl_vadd.hw_emu.xilinx_u250_gen3x16_xdma_3_1_202020_1.xclbin'\nINFO: &#91;HW-EMU 01] Hardware emulation runs simulation underneath. Using a large data set will result in long simulation times. It is recommended that a small dataset is used for faster execution. The flow uses approximate models for Global memories and interconnect and hence the performance data generated is approximate.\nconfiguring dataflow mode with ert polling\nscheduler config ert(1), dataflow(1), slots(16), cudma(0), cuisr(0), cdma(0), cus(2)\nTEST WITH TWO KERNELS PASSED\nINFO::&#91; Vitis-EM 22 ] &#91;Time elapsed: 0 minute(s) 32 seconds, Emulation time: 0.278837 ms]\nData transfer between kernel(s) and global memory(s)\nkrnl_vadd_1:m_axi_gmem-DDR&#91;1]          RD = 32.000 KB              WR = 0.000 KB        \nkrnl_vadd_1:m_axi_gmem1-DDR&#91;1]          RD = 0.000 KB               WR = 16.000 KB       \nrtl_kernel_wizard_0_1:m00_axi-DDR&#91;1]          RD = 16.000 KB              WR = 16.000 KB       \n\nINFO: &#91;HW-EMU 06-0] Waiting for the simulator process to exit\nINFO: &#91;HW-EMU 06-1] All the simulator processes exited successfully<\/code><\/pre>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"290\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image12-1024x290.png\" alt=\"\" class=\"wp-image-412\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image12-1024x290.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image12-300x85.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image12-768x218.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image12.png 1264w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>View the Application Timeline report in the Vitis analyzer.<\/p>\n\n\n\n<p><code>vitis_analyzer xclbin.run_summary<\/code><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"478\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image13-1024x478.png\" alt=\"\" class=\"wp-image-413\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image13-1024x478.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image13-300x140.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image13-768x358.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image13.png 1321w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"556\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image14-1024x556.png\" alt=\"\" class=\"wp-image-414\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image14-1024x556.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image14-300x163.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image14-768x417.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image14.png 1316w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"605\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image15-1024x605.png\" alt=\"\" class=\"wp-image-415\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image15-1024x605.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image15-300x177.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image15-768x453.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image15.png 1316w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"857\" height=\"593\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image16.png\" alt=\"\" class=\"wp-image-416\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image16.png 857w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image16-300x208.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image16-768x531.png 768w\" sizes=\"auto, (max-width: 857px) 100vw, 857px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p>After reviewing, close the Application Timeline, and exit Vitis analyzer.<\/p>\n\n\n\n<h1 class=\"has-medium-font-size wp-block-heading\">RTL kernel as Vivado project<\/h1>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"511\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-1024x511.png\" alt=\"\" class=\"wp-image-417\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-1024x511.png 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-300x150.png 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-768x384.png 768w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-1536x767.png 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17-500x250.png 500w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2022\/03\/image17.png 1632w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Reference screenshot<\/figcaption><\/figure>\n\n\n\n<p class=\"has-text-align-center\"><strong><mark style=\"background-color:#abb8c3\" class=\"has-inline-color has-black-color\">==================== END ====================<\/mark><\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"<p>For Turnkey Accelerator System (TKAS-D2101) with Alveo U250 Card and Xilinx Vitis\u2122 Unified Software Platform 2021.1 Based on Xilinx&#8217;s Vitis\u2122 Application Acceleration Development Flow Tutorials: Mixing C++ and RTL Kernels This tutorial is split into two parts: In the first part, you will build an application (host and kernel) with one C++ based kernel. The host code, including the kernel&#46;&#46;&#46;<\/p>\n","protected":false},"author":1,"featured_media":396,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[11],"tags":[],"class_list":["post-338","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-accelerated-computing-tutorial"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/338","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=338"}],"version-history":[{"count":51,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/338\/revisions"}],"predecessor-version":[{"id":418,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/338\/revisions\/418"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/396"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=338"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=338"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=338"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}