{"id":3922,"date":"2026-10-22T15:27:18","date_gmt":"2026-10-22T08:27:18","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=3922"},"modified":"2026-10-22T16:04:13","modified_gmt":"2026-10-22T09:04:13","slug":"case-study-validating-nvme-ssd-sustained-throughput-and-buffer-needs-for-continuous-data-logging","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2026\/10\/22\/case-study-validating-nvme-ssd-sustained-throughput-and-buffer-needs-for-continuous-data-logging\/","title":{"rendered":"Case Study: Validating NVMe SSD Sustained Throughput and Buffer Needs for Continuous Data Logging"},"content":{"rendered":"\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"338\" src=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-1024x338.jpg\" alt=\"\" class=\"wp-image-3934\" srcset=\"https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-1024x338.jpg 1024w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-300x99.jpg 300w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-766x253.jpg 766w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-1536x507.jpg 1536w, https:\/\/dgway.com\/blog_E\/wp-content\/uploads\/2026\/10\/banner_Resize-2048x677.jpg 2048w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<!-- Block 0: Global Master CSS & Base Wrapper Open -->\n<style>\n  .dg-blog-wrapper {\n    font-family: -apple-system, BlinkMacSystemFont, \"Segoe UI\", Roboto, Oxygen-Sans, Ubuntu, Cantarell, \"Helvetica Neue\", sans-serif;\n    color: #334155;\n    background-color: #ffffff;\n    line-height: 1.7;\n    max-width: 1000px;\n    margin: 0 auto;\n    padding: 20px 15px;\n  }\n  .dg-blog-wrapper p, .dg-blog-wrapper li {\n    font-size: 1.8rem !important;\n    color: #334155;\n  }\n  .dg-blog-wrapper h2 {\n    font-size: 2.8rem !important;\n    color: #0f172a;\n    font-weight: 700;\n    margin-top: 40px;\n    margin-bottom: 20px;\n    display: flex;\n    align-items: center;\n    gap: 14px;\n    border-bottom: 2px solid #e2e8f0;\n    padding-bottom: 12px;\n  }\n  .dg-blog-wrapper h3 {\n    font-size: 2.4rem !important;\n    color: #0369a1;\n    font-weight: 600;\n    margin-top: 25px;\n    margin-bottom: 15px;\n  }\n  .dg-blog-wrapper h4 {\n    font-size: 2.0rem !important;\n    color: #0f172a;\n    font-weight: 600;\n    margin-top: 15px;\n    margin-bottom: 10px;\n  }\n  .dg-lead-text {\n    font-size: 2.0rem !important;\n    color: #475569;\n    line-height: 1.8;\n    background: #f0f9ff;\n    border-left: 5px solid #0284c7;\n    padding: 20px 24px;\n    border-radius: 4px;\n    margin-bottom: 30px;\n  }\n  .dg-icon-svg {\n    width: 36px;\n    height: 36px;\n    stroke: #0284c7;\n    flex-shrink: 0;\n  }\n  .dg-img-wrapper {\n    text-align: center;\n    margin: 30px 0;\n    background: #f8fafc;\n    padding: 16px;\n    border-radius: 8px;\n    border: 1px solid #e2e8f0;\n  }\n  .dg-img-wrapper img {\n    max-width: 100%;\n    height: auto;\n    border-radius: 6px;\n  }\n  .dg-img-caption {\n    font-size: 1.5rem !important;\n    color: #64748b;\n    margin-top: 10px;\n    font-style: italic;\n  }\n  .dg-comparison-grid {\n    display: grid;\n    grid-template-columns: 1fr 1fr;\n    gap: 20px;\n    margin: 25px 0;\n  }\n  @media (max-width: 768px) {\n    .dg-comparison-grid { grid-template-columns: 1fr; }\n  }\n  .dg-comp-card {\n    padding: 24px;\n    border-radius: 8px;\n    border: 1px solid #e2e8f0;\n    background: #ffffff;\n  }\n  .dg-comp-challenge {\n    border-top: 4px solid #ea580c;\n    background: #fffaf5;\n  }\n  .dg-comp-solution {\n    border-top: 4px solid #0284c7;\n    background: #f0f9ff;\n  }\n  .dg-comp-card h4 {\n    margin-top: 0;\n    display: flex;\n    align-items: center;\n    gap: 8px;\n  }\n  .dg-metrics-row {\n    display: flex;\n    gap: 20px;\n    margin: 30px 0;\n    flex-wrap: wrap;\n  }\n  .dg-metric-card {\n    flex: 1;\n    min-width: 240px;\n    background: #f8fafc;\n    border: 1px solid #bae6fd;\n    border-radius: 8px;\n    padding: 24px;\n    text-align: center;\n  }\n  .dg-metric-val {\n    font-size: 3.6rem !important;\n    font-weight: 800;\n    color: #02b073;\n    line-height: 1.1;\n    margin-bottom: 8px;\n  }\n  .dg-metric-lbl {\n    font-size: 1.6rem !important;\n    color: #475569;\n    font-weight: 500;\n  }\n  .dg-cards-3col {\n    display: flex;\n    gap: 20px;\n    margin: 25px 0;\n    flex-wrap: wrap;\n  }\n  .dg-feature-card {\n    flex: 1;\n    min-width: 260px;\n    background: #ffffff;\n    border: 1px solid #e2e8f0;\n    border-radius: 8px;\n    padding: 20px;\n    box-shadow: 0 2px 4px rgba(0,0,0,0.02);\n  }\n  .dg-feature-card h4 {\n    color: #0369a1;\n    margin-top: 0;\n  }\n  .dg-highlight-box {\n    background: #e0f2fe;\n    border: 1px solid #bae6fd;\n    border-radius: 8px;\n    padding: 20px 24px;\n    margin: 25px 0;\n  }\n  .dg-cta-container {\n    background: linear-gradient(135deg, #0369a1 0%, #0284c7 100%);\n    color: #ffffff;\n    padding: 35px 30px;\n    border-radius: 10px;\n    margin-top: 40px;\n    text-align: center;\n  }\n  .dg-cta-container h3 {\n    color: #ffffff !important;\n    margin-top: 0;\n    font-size: 2.6rem !important;\n  }\n  .dg-cta-container p {\n    color: #e0f2fe !important;\n  }\n  .dg-btn-group {\n    display: flex;\n    justify-content: center;\n    gap: 15px;\n    margin-top: 25px;\n    flex-wrap: wrap;\n  }\n  .dg-btn-primary {\n    display: inline-block;\n    background-color: #ffffff;\n    color: #0369a1 !important;\n    font-weight: 700;\n    font-size: 1.7rem !important;\n    padding: 14px 28px;\n    border-radius: 6px;\n    text-decoration: none;\n    transition: background-color 0.2s;\n  }\n  .dg-btn-primary:hover {\n    background-color: #f0f9ff;\n  }\n  .dg-btn-outline {\n    display: inline-block;\n    background-color: transparent;\n    color: #ffffff !important;\n    font-weight: 600;\n    font-size: 1.7rem !important;\n    padding: 14px 28px;\n    border-radius: 6px;\n    text-decoration: none;\n    border: 2px solid #ffffff;\n  }\n  .dg-btn-outline:hover {\n    background-color: rgba(255,255,255,0.1);\n  }\n<\/style>\n\n<div class=\"dg-blog-wrapper\"><\/div>\n\n\n\n<!-- Block 1: Lead Introduction & Case Study Overview -->\n<div class=\"dg-lead-text\">\n  <strong>Case Study Overview:<\/strong> In mission-critical edge recording and continuous instrumentation, relying on peak SSD datasheets often results in catastrophic data loss. This case study demonstrates how empirical testing on the <strong>AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105 Evaluation Kit<\/strong> using Design Gateway\u2019s <strong>NVMe\u2122 SSD Characteristic Test Platform<\/strong> validates sustained read\/write throughput and precisely identifies external DDR buffer requirements.\n<\/div>\n\n<p>\n  Modern high-speed data acquisition systems\u2014ranging from radar sensing to multi-camera vision platforms\u2014require consistent, deterministic storage throughput. However, system architects frequently encounter unexpected bandwidth drops during continuous operations. Understanding drive characteristics under long-duration workloads is the key to achieving robust system integration without expensive over-provisioning.\n<\/p>\n\n\n\n<!-- Additional Section: Real-World Mission-Critical Applications (\u0e41\u0e19\u0e27\u0e17\u0e32\u0e07\u0e17\u0e35\u0e48 1 - \u0e02\u0e22\u0e32\u0e22\u0e01\u0e25\u0e48\u0e2d\u0e07\u0e25\u0e48\u0e32\u0e07\u0e40\u0e15\u0e47\u0e21\u0e04\u0e27\u0e32\u0e21\u0e01\u0e27\u0e49\u0e32\u0e07) -->\n<div style=\"margin: 30px 0;\">\n  <h2>\n<h2 style=\"display: flex !important; align-items: center !important; gap: 14px !important; margin-top: 40px; margin-bottom: 20px; border-bottom: 2px solid #e2e8f0; padding-bottom: 12px;\">\n    <svg style=\"width: 28px; height: 28px; stroke: #0284c7; vertical-align: middle; margin-right: 8px;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n      <path d=\"M22 12h-4l-3 9L9 3l-3 9H2\"><\/path>\n    <\/svg>\n    Real-World Impact: Where Zero Data Loss is Mandatory\n  <\/h2>\n  <p>\n    In non-critical consumer devices, temporary write latency spikes are easily masked by OS-level memory caching. However, mission-critical edge instrumentation cannot tolerate even microsecond-level storage stalls:\n  <\/p>\n  \n  <div style=\"display: grid; grid-template-columns: repeat(2, 1fr); gap: 16px; margin-top: 20px;\">\n    <!-- \u0e01\u0e25\u0e48\u0e2d\u0e07\u0e17\u0e35\u0e48 1: Autonomous Vehicles & ADAS -->\n    <div style=\"background: #c8e1fa; border: 1px solid #e2e8f0; border-left: 4px solid #0284c7; padding: 18px 20px; border-radius: 6px;\">\n      <h4 style=\"margin-top: 0; color: #0369a1;\">Autonomous Vehicles &amp; ADAS<\/h4>\n      <p style=\"font-size: 1.6rem !important; margin-bottom: 0;\">\n        Simultaneous ingestion from multiple 4K raw HDR camera sensors, LiDAR arrays, and radar streams requires sustained continuous logging rates of multiple GB\/s without a single dropped frame during on-road safety validation.\n      <\/p>\n    <\/div>\n\n    <!-- \u0e01\u0e25\u0e48\u0e2d\u0e07\u0e17\u0e35\u0e48 2: Defense & Aerospace RF Capture -->\n    <div style=\"background: #c8e1fa; border: 1px solid #e2e8f0; border-left: 4px solid #0284c7; padding: 18px 20px; border-radius: 6px;\">\n      <h4 style=\"margin-top: 0; color: #0369a1;\">Defense &amp; Aerospace RF Capture<\/h4>\n      <p style=\"font-size: 1.6rem !important; margin-bottom: 0;\">\n        Direct RF signal digitizing and high-speed spectrum logging demand uninterrupted sequential writes. Any SSD buffer overflow results in corrupted telemetry or unrecoverable radar waveforms.\n      <\/p>\n    <\/div>\n\n    <!-- \u0e01\u0e25\u0e48\u0e2d\u0e07\u0e17\u0e35\u0e48 3: 100G\/400G Network Packet Capture (\u0e02\u0e22\u0e32\u0e22\u0e40\u0e15\u0e47\u0e21 2 \u0e04\u0e2d\u0e25\u0e31\u0e21\u0e19\u0e4c\u0e14\u0e49\u0e32\u0e19\u0e25\u0e48\u0e32\u0e07) -->\n    <div style=\"grid-column: span 2; background: #c8e1fa; border: 1px solid #e2e8f0; border-left: 4px solid #0284c7; padding: 18px 20px; border-radius: 6px;\">\n      <h4 style=\"margin-top: 0; color: #0369a1;\">100G\/400G Network Packet Capture<\/h4>\n      <p style=\"font-size: 1.6rem !important; margin-bottom: 0;\">\n        Line-rate network traffic monitoring and deep packet inspection (DPI) platforms mandate predictable write endurance and zero dropped packets across continuous multi-terabyte recording sessions.\n      <\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<!-- \u0e2a\u0e44\u0e15\u0e25\u0e4c\u0e40\u0e1e\u0e34\u0e48\u0e21\u0e40\u0e15\u0e34\u0e21\u0e2a\u0e33\u0e2b\u0e23\u0e31\u0e1a\u0e17\u0e33\u0e43\u0e2b\u0e49 Responsive \u0e1a\u0e19\u0e21\u0e37\u0e2d\u0e16\u0e37\u0e2d (\u0e43\u0e2b\u0e49\u0e01\u0e25\u0e31\u0e1a\u0e21\u0e32\u0e0b\u0e49\u0e2d\u0e19\u0e01\u0e31\u0e19 1 \u0e04\u0e2d\u0e25\u0e31\u0e21\u0e19\u0e4c) -->\n<style>\n  @media (max-width: 768px) {\n    div[style*=\"display: grid\"] {\n      grid-template-columns: 1fr !important;\n    }\n    div[style*=\"grid-column: span 2\"] {\n      grid-column: span 1 !important;\n    }\n  }\n<\/style>\n\n\n\n<!-- Block 2: Section 1 - Challenge & SSD Behaviors -->\n<h2 style=\"display: flex !important; align-items: center !important; gap: 14px !important; margin-top: 40px; margin-bottom: 20px; border-bottom: 2px solid #e2e8f0; padding-bottom: 12px;\">\n  <svg style=\"width: 36px; height: 36px; stroke: #0284c7; flex-shrink: 0;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n    <path d=\"M10.29 3.86L1.82 18a2 2 0 0 0 1.71 3h16.94a2 2 0 0 0 1.71-3L13.71 3.86a2 2 0 0 0-3.42 0z\"><\/path>\n    <line x1=\"12\" y1=\"9\" x2=\"12\" y2=\"13\"><\/line>\n    <line x1=\"12\" y1=\"17\" x2=\"12.01\" y2=\"17\"><\/line>\n  <\/svg>\n  <span>The Challenge: Sustained Write Collapse<\/span>\n<\/h2>\n\n<p>\n  Not all NVMe\u2122 SSDs behave equally under continuous, long-term write pressure. While datasheets boast multi-gigabyte speeds, those metrics typically measure short-burst operations.\n<\/p>\n\n<div class=\"dg-comparison-grid\">\n  <div class=\"dg-comp-card dg-comp-challenge\">\n    <h4 style=\"color: #c2410c;\">Consumer SSDs (Burst-Optimized)<\/h4>\n    <p>\n      Rely heavily on internal SLC cache regions to boost short-term benchmark performance. Once the cache buffer is saturated, throughput plummets dramatically and fluctuates unpredictably, making them prone to FIFO overflows in real-time streaming.\n    <\/p>\n  <\/div>\n  <div class=\"dg-comp-card dg-comp-solution\">\n    <h4 style=\"color: #0369a1;\">Enterprise SSDs (Sustained Workloads)<\/h4>\n    <p>\n      Engineered with heavy over-provisioning and advanced wear-leveling algorithms to maintain steady sequential write performance over hours of continuous recording, guaranteeing deterministic Quality of Service (QoS).\n    <\/p>\n  <\/div>\n<\/div>\n\n<div class=\"dg-img-wrapper\">\n  <img decoding=\"async\" src=\"https:\/\/www.dgway.com\/solutions\/Sustained-Rate_DataLogging\/dataflow.png\" alt=\"NVMe-IP with DDR System Overview\">\n  <div class=\"dg-img-caption\">Figure 1: High-Speed Continuous Data Logging Architecture using Design Gateway NVMe-IP Core and DDR Memory Buffer.<\/div>\n<\/div>\n\n\n\n<!-- Block 3: Section 2 - Test Platform & Methodology -->\n<h2 style=\"display: flex !important; align-items: center !important; gap: 14px !important; margin-top: 40px; margin-bottom: 20px; border-bottom: 2px solid #e2e8f0; padding-bottom: 12px;\">\n  <svg style=\"width: 36px; height: 36px; stroke: #0284c7; flex-shrink: 0;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n    <rect x=\"2\" y=\"3\" width=\"20\" height=\"14\" rx=\"2\" ry=\"2\"><\/rect>\n    <line x1=\"8\" y1=\"21\" x2=\"16\" y2=\"21\"><\/line>\n    <line x1=\"12\" y1=\"17\" x2=\"12\" y2=\"21\"><\/line>\n  <\/svg>\n  <span>The Solution: NVMe SSD Characteristic Test Platform<\/span>\n<\/h2>\n<p>\n  To eliminate performance guesswork before PCB fabrication, Design Gateway developed an FPGA-centric evaluation platform running entirely in pure hardware logic (no embedded OS, CPU, or software driver bottlenecks).\n<\/p>\n\n<!-- Enhanced Feature Cards with Inline Icons -->\n<div class=\"dg-cards-3col\" style=\"display: flex; gap: 20px; margin: 25px 0; flex-wrap: wrap;\">\n  <!-- Card 1: Speed Setting -->\n  <div class=\"dg-feature-card\" style=\"flex: 1; min-width: 260px; background: #ffffff; border: 1px solid #e2e8f0; border-radius: 8px; padding: 22px 20px; box-shadow: 0 2px 4px rgba(0,0,0,0.02);\">\n    <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 12px;\">\n      <div style=\"width: 40px; height: 40px; border-radius: 8px; background: #f0f9ff; display: flex; align-items: center; justify-content: center; flex-shrink: 0;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><circle cx=\"12\" cy=\"12\" r=\"10\"><\/circle><polyline points=\"12 6 12 12 16 14\"><\/polyline><\/svg>\n      <\/div>\n      <h4 style=\"margin: 0; color: #0369a1; font-size: 2.0rem !important;\">1. Parametric Speed Setting<\/h4>\n    <\/div>\n    <p style=\"font-size: 1.6rem !important; color: #475569; margin: 0;\">\n      Users configure precise target write\/read throughput rates to systematically stress-test the drive under realistic streaming bandwidth demands.\n    <\/p>\n  <\/div>\n\n  <!-- Card 2: Buffer Sizing -->\n  <div class=\"dg-feature-card\" style=\"flex: 1; min-width: 260px; background: #ffffff; border: 1px solid #e2e8f0; border-radius: 8px; padding: 22px 20px; box-shadow: 0 2px 4px rgba(0,0,0,0.02);\">\n    <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 12px;\">\n      <div style=\"width: 40px; height: 40px; border-radius: 8px; background: #f0f9ff; display: flex; align-items: center; justify-content: center; flex-shrink: 0;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><line x1=\"4\" y1=\"21\" x2=\"4\" y2=\"14\"><\/line><line x1=\"4\" y1=\"10\" x2=\"4\" y2=\"3\"><\/line><line x1=\"12\" y1=\"21\" x2=\"12\" y2=\"12\"><\/line><line x1=\"12\" y1=\"8\" x2=\"12\" y2=\"3\"><\/line><line x1=\"20\" y1=\"21\" x2=\"20\" y2=\"16\"><\/line><line x1=\"20\" y1=\"12\" x2=\"20\" y2=\"3\"><\/line><line x1=\"1\" y1=\"14\" x2=\"7\" y2=\"14\"><\/line><line x1=\"9\" y1=\"8\" x2=\"15\" y2=\"8\"><\/line><line x1=\"17\" y1=\"16\" x2=\"23\" y2=\"16\"><\/line><\/svg>\n      <\/div>\n      <h4 style=\"margin: 0; color: #0369a1; font-size: 2.0rem !important;\">2. Configurable DDR Buffer<\/h4>\n    <\/div>\n    <p style=\"font-size: 1.6rem !important; color: #475569; margin: 0;\">\n      Allows engineers to dynamically vary intermediate memory buffer sizes to determine how much reserve capacity is required to smooth out drive latency spikes.\n    <\/p>\n  <\/div>\n\n  <!-- Card 3: Pass\/Fail -->\n  <div class=\"dg-feature-card\" style=\"flex: 1; min-width: 260px; background: #ffffff; border: 1px solid #e2e8f0; border-radius: 8px; padding: 22px 20px; box-shadow: 0 2px 4px rgba(0,0,0,0.02);\">\n    <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 12px;\">\n      <div style=\"width: 40px; height: 40px; border-radius: 8px; background: #f0f9ff; display: flex; align-items: center; justify-content: center; flex-shrink: 0;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><path d=\"M22 11.08V12a10 10 0 1 1-5.93-9.14\"><\/path><polyline points=\"22 4 12 14.01 9 11.01\"><\/polyline><\/svg>\n      <\/div>\n      <h4 style=\"margin: 0; color: #0369a1; font-size: 2.0rem !important;\">3. Pass \/ Fail Validation<\/h4>\n    <\/div>\n    <p style=\"font-size: 1.6rem !important; color: #475569; margin: 0;\">\n      Delivers an immediate Pass\/Fail status indicating whether the drive maintained uninterrupted throughput without triggering a buffer overflow condition.\n    <\/p>\n  <\/div>\n<\/div>\n\n\n\n<!-- Block 4: Section 3 - Benchmarks & Results -->\n<h2 style=\"display: flex !important; align-items: center !important; gap: 14px !important; margin-top: 40px; margin-bottom: 20px; border-bottom: 2px solid #e2e8f0; padding-bottom: 12px;\">\n  <svg style=\"width: 36px; height: 36px; stroke: #0284c7; flex-shrink: 0;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n    <polyline points=\"22 12 18 12 15 21 9 3 6 12 2 12\"><\/polyline>\n  <\/svg>\n  <span>Empirical Results: Identifying the Critical Buffer Threshold<\/span>\n<\/h2>\n\n<p>\n  The platform was evaluated on the <strong>AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105 Evaluation Kit<\/strong> equipped with a <strong>Design Gateway AB18-PCIe\u00aeX16 adapter<\/strong> and an <strong>Intel\u00ae Optane\u2122 SSD 900P<\/strong>. A continuous 280 GB LFSR payload was streamed across varying target speeds.\n<\/p>\n\n<!-- Additional Section: Hardware Test Setup & Methodology -->\n<!-- Enhanced Section: Hardware Test Setup (2x2 Spec Cards with SVGs) -->\n<div style=\"margin: 35px 0;\">\n  <h3>\n    <svg style=\"width: 28px; height: 28px; stroke: #0284c7; vertical-align: middle; margin-right: 8px;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n      <circle cx=\"12\" cy=\"12\" r=\"3\"><\/circle>\n      <path d=\"M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z\"><\/path>\n    <\/svg>\n    Experimental Methodology &amp; Hardware Setup\n  <\/h3>\n  \n  <p style=\"margin-bottom: 20px;\">\n    To establish a reliable performance baseline, the evaluation benchmarked continuous sequential writing without host CPU intervention:\n  <\/p>\n\n  <div style=\"display: grid; grid-template-columns: repeat(2, 1fr); gap: 16px;\">\n    <!-- Card 1: FPGA Platform -->\n    <div style=\"background: #f8fafc; border: 1px solid #e2e8f0; border-top: 3px solid #0284c7; border-radius: 6px; padding: 18px 20px;\">\n      <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 8px;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><rect x=\"4\" y=\"4\" width=\"16\" height=\"16\" rx=\"2\" ry=\"2\"><\/rect><rect x=\"9\" y=\"9\" width=\"6\" height=\"6\"><\/rect><line x1=\"9\" y1=\"1\" x2=\"9\" y2=\"4\"><\/line><line x1=\"15\" y1=\"1\" x2=\"15\" y2=\"4\"><\/line><line x1=\"9\" y1=\"20\" x2=\"9\" y2=\"23\"><\/line><line x1=\"15\" y1=\"20\" x2=\"15\" y2=\"23\"><\/line><line x1=\"20\" y1=\"9\" x2=\"23\" y2=\"9\"><\/line><line x1=\"20\" y1=\"14\" x2=\"23\" y2=\"14\"><\/line><line x1=\"1\" y1=\"9\" x2=\"4\" y2=\"9\"><\/line><line x1=\"1\" y1=\"14\" x2=\"4\" y2=\"14\"><\/line><\/svg>\n        <h4 style=\"margin: 0; color: #0369a1; font-size: 1.9rem !important;\">FPGA Target Platform<\/h4>\n      <\/div>\n      <p style=\"font-size: 1.6rem !important; margin: 0; color: #475569;\">\n        <strong>AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105<\/strong> Evaluation Kit utilizing pure RTL logic (Design Gateway NVMe\u2122-IP core with external DDR4 memory buffer).\n      <\/p>\n    <\/div>\n\n    <!-- Card 2: Storage Interface -->\n    <div style=\"background: #f8fafc; border: 1px solid #e2e8f0; border-top: 3px solid #0284c7; border-radius: 6px; padding: 18px 20px;\">\n      <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 8px;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><rect x=\"2\" y=\"5\" width=\"20\" height=\"14\" rx=\"2\"><\/rect><line x1=\"2\" y1=\"10\" x2=\"22\" y2=\"10\"><\/line><\/svg>\n        <h4 style=\"margin: 0; color: #0369a1; font-size: 1.9rem !important;\">Storage Interface<\/h4>\n      <\/div>\n      <p style=\"font-size: 1.6rem !important; margin: 0; color: #475569;\">\n        <strong>Design Gateway AB18-PCIe\u00aeX16<\/strong> adapter board directly hosting an <strong>Intel\u00ae Optane\u2122 SSD 900P<\/strong> via PCIe\u00ae Gen3 x4 interface.\n      <\/p>\n    <\/div>\n\n    <!-- Card 3: Why Optane SSD -->\n    <div style=\"background: #f8fafc; border: 1px solid #e2e8f0; border-top: 3px solid #0284c7; border-radius: 6px; padding: 18px 20px;\">\n      <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 8px;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><ellipse cx=\"12\" cy=\"5\" rx=\"9\" ry=\"3\"><\/ellipse><path d=\"M21 12c0 1.66-4 3-9 3s-9-1.34-9-3\"><\/path><path d=\"M3 5v14c0 1.66 4 3 9 3s9-1.34 9-3V5\"><\/path><\/svg>\n        <h4 style=\"margin: 0; color: #0369a1; font-size: 1.9rem !important;\">Why Intel\u00ae Optane\u2122<\/h4>\n      <\/div>\n      <p style=\"font-size: 1.6rem !important; margin: 0; color: #475569;\">\n        3D XPoint architecture provides exceptionally flat write latencies without SLC-cache depletion, measuring pure FPGA-to-SSD throughput limits rather than drive throttling.\n      <\/p>\n    <\/div>\n\n    <!-- Card 4: Stress Pattern & Payload -->\n    <div style=\"background: #f8fafc; border: 1px solid #e2e8f0; border-top: 3px solid #0284c7; border-radius: 6px; padding: 18px 20px;\">\n      <div style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 8px;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><polyline points=\"22 12 18 12 15 21 9 3 6 12 2 12\"><\/polyline><\/svg>\n        <h4 style=\"margin: 0; color: #0369a1; font-size: 1.9rem !important;\">Stress Workload<\/h4>\n      <\/div>\n      <p style=\"font-size: 1.6rem !important; margin: 0; color: #475569;\">\n        Continuous <strong>280 GB<\/strong> pseudo-random LFSR stream tested across stepped bandwidth targets (1,000 to 2,800 MB\/s) with real-time peak DDR buffer monitoring.\n      <\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<style>\n  @media (max-width: 768px) {\n    div[style*=\"display: grid; grid-template-columns: repeat(2, 1fr)\"] {\n      grid-template-columns: 1fr !important;\n    }\n  }\n<\/style>\n\n<div class=\"dg-metrics-row\">\n  <div class=\"dg-metric-card\">\n    <div class=\"dg-metric-val\">2,800 MB\/s<\/div>\n    <div class=\"dg-metric-lbl\">Max Sustained Write Verified<\/div>\n  <\/div>\n  <div class=\"dg-metric-card\">\n    <div class=\"dg-metric-val\">1,500 \u2013 2,285<\/div>\n    <div class=\"dg-metric-lbl\">Critical Speed Threshold (MB\/s)<\/div>\n  <\/div>\n  <div class=\"dg-metric-card\">\n    <div class=\"dg-metric-val\">0% CPU \/ OS<\/div>\n    <div class=\"dg-metric-lbl\">Pure Hardware FPGA Implementation<\/div>\n  <\/div>\n<\/div>\n\n<div class=\"dg-highlight-box\">\n  <h4>Key Architecture Insight: Internal FIFO vs. External DDR<\/h4>\n  <p>\n    The test data revealed an abrupt behavioral shift: below <strong>1,500 MB\/s<\/strong>, maximum buffer utilization stayed within standard kilobyte ranges, indicating that an internal FPGA Block RAM \/ UltraRAM FIFO is fully sufficient. However, crossing beyond <strong>2,285 MB\/s<\/strong> caused peak buffer demand to scale sharply into hundreds of megabytes. At these high data rates, incorporating external DDR memory becomes mandatory to absorb extended SSD write-cycle latencies.\n  <\/p>\n<\/div>\n\n<div class=\"dg-img-wrapper\">\n  <img decoding=\"async\" src=\"https:\/\/www.dgway.com\/solutions\/Sustained-Rate_DataLogging\/perfresult.png\" alt=\"Peak DDR Buffer Usage vs Sustained Write Speed\">\n  <div class=\"dg-img-caption\">Figure 3: Measured Peak Buffer Usage scaling sharply between 1,500 MB\/s and 2,285 MB\/s.<\/div>\n<\/div>\n\n\n\n<!-- Block 5: Section 4 - Conclusion, Replication & Resources -->\n<h2 style=\"display: flex !important; align-items: center !important; gap: 14px !important; margin-top: 40px; margin-bottom: 20px; border-bottom: 2px solid #e2e8f0; padding-bottom: 12px;\">\n  <svg style=\"width: 36px; height: 36px; stroke: #0284c7; flex-shrink: 0;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n    <path d=\"M22 11.08V12a10 10 0 1 1-5.93-9.14\"><\/path>\n    <polyline points=\"22 4 12 14.01 9 11.01\"><\/polyline>\n  <\/svg>\n  <span>Conclusion: System Right-Sizing &amp; Verification<\/span>\n<\/h2>\n\n<p>\n  As demonstrated in this case study, continuous sustained-rate recording cannot rely solely on headline SSD specs. Empirical testing on the <strong>AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105<\/strong> clearly reveals drive latency characteristics and identifies the exact threshold where external DDR becomes mandatory. Sizing memory buffers based on actual benchmark data prevents costly hardware re-spins, ensures zero data loss, and eliminates over-engineering.\n<\/p>\n\n<!-- Case Study Technical Resources -->\n<div style=\"margin: 30px 0;\">\n  <h3 style=\"margin-bottom: 18px;\">Case Study Verification Resources<\/h3>\n  \n  <div style=\"display: flex; flex-direction: column; gap: 12px;\">\n    <!-- Resource 1: Reference Design Document -->\n    <a href=\"https:\/\/dgway.com\/products\/IP\/NVMe-IP\/dg_nvmeddr_refdesign_en\/\" target=\"_blank\" rel=\"noopener\" style=\"display: flex; align-items: center; gap: 14px; padding: 16px 20px; background-color: #f8fafc; border: 1px solid #bae6fd; border-radius: 6px; text-decoration: none; color: #0369a1; font-size: 1.8rem; font-weight: 600; transition: background 0.2s;\">\n      <svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><path d=\"M14 2H6a2 2 0 0 0-2 2v16a2 2 0 0 0 2 2h12a2 2 0 0 0 2-2V8z\"><\/path><polyline points=\"14 2 14 8 20 8\"><\/polyline><line x1=\"16\" y1=\"13\" x2=\"8\" y2=\"13\"><\/line><line x1=\"16\" y1=\"17\" x2=\"8\" y2=\"17\"><\/line><polyline points=\"10 9 9 9 8 9\"><\/polyline><\/svg>\n      Reference Design Document\n    <\/a>\n\n    <!-- Resource 2: Demo Instruction Manual -->\n    <a href=\"https:\/\/dgway.com\/products\/IP\/NVMe-IP\/dg_nvmeddr_instruction_en\/\" target=\"_blank\" rel=\"noopener\" style=\"display: flex; align-items: center; gap: 14px; padding: 16px 20px; background-color: #f8fafc; border: 1px solid #bae6fd; border-radius: 6px; text-decoration: none; color: #0369a1; font-size: 1.8rem; font-weight: 600; transition: background 0.2s;\">\n      <svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><path d=\"M16 4h2a2 2 0 0 1 2 2v14a2 2 0 0 1-2 2H6a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h2\"><\/path><rect x=\"8\" y=\"2\" width=\"8\" height=\"4\" rx=\"1\" ry=\"1\"><\/rect><\/svg>\n      Demo Instruction Manual\n    <\/a>\n\n    <!-- Resource 3: NVMe-IP Core Product Page -->\n    <a href=\"https:\/\/www.dgway.com\/NVMe-IP_X_E.html\" target=\"_blank\" rel=\"noopener\" style=\"display: flex; align-items: center; gap: 14px; padding: 16px 20px; background-color: #f8fafc; border: 1px solid #bae6fd; border-radius: 6px; text-decoration: none; color: #0369a1; font-size: 1.8rem; font-weight: 600; transition: background 0.2s;\">\n      <svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><path d=\"M10 13a5 5 0 0 0 7.54.54l3-3a5 5 0 0 0-7.07-7.07l-1.72 1.71\"><\/path><path d=\"M14 11a5 5 0 0 0-7.54-.54l-3 3a5 5 0 0 0 7.07 7.07l1.71-1.71\"><\/path><\/svg>\n      NVMe\u2122-IP Core Product Page\n    <\/a>\n  <\/div>\n<\/div>\n\n<!-- Section: Hardware Demonstration Video (Custom Card Matching Solution Page Style) -->\n<div style=\"margin: 35px 0;\">\n  <h3>\n    <svg style=\"width: 28px; height: 28px; stroke: #0284c7; vertical-align: middle; margin-right: 8px;\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"currentColor\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\">\n      <polygon points=\"5 3 19 12 5 21 5 3\"><\/polygon>\n    <\/svg>\n    Live Demonstration: Sustained Rate &amp; Buffer Verification\n  <\/h3>\n  <p>\n    Watch the <strong>NVMe\u2122 SSD Characteristic Test Platform<\/strong> in action on the <strong>AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105<\/strong> board, demonstrating real-time throughput tracking, pass\/fail evaluation, and dynamic DDR buffer usage measurement:\n  <\/p>\n\n  <!-- Video Card Container Matching Solution Page -->\n  <div style=\"background-color: #0c1a30; border: 1px solid #1e2e4a; border-radius: 8px; padding: 24px 20px 30px 20px; max-width: 820px; margin: 25px auto; text-align: center; box-shadow: 0 4px 20px rgba(0,0,0,0.25);\">\n    \n    <!-- Top Label -->\n    <div style=\"color: #38bdf8; font-size: 1.5rem !important; font-weight: 800; letter-spacing: 1.5px; text-transform: uppercase; margin-bottom: 18px;\">\n      DEMO VIDEO\n    <\/div>\n\n    <!-- Thumbnail Wrapper with Red Play Button -->\n    <a href=\"https:\/\/www.youtube.com\/watch?v=Zwk0r-TVuNA\" target=\"_blank\" rel=\"noopener\" style=\"display: block; position: relative; max-width: 740px; margin: 0 auto; text-decoration: none; border-radius: 6px; overflow: hidden; border: 1px solid rgba(255,255,255,0.1); box-shadow: 0 6px 18px rgba(0,0,0,0.4);\">\n      <img decoding=\"async\" src=\"https:\/\/img.youtube.com\/vi\/Zwk0r-TVuNA\/maxresdefault.jpg\" alt=\"NVMe-IP DDR Reference Design Demo on AMD KCU105\" style=\"width: 100%; height: auto; display: block;\">\n      \n      <!-- YouTube Style Red Play Icon -->\n      <div style=\"position: absolute; top: 50%; left: 50%; transform: translate(-50%, -50%); width: 68px; height: 48px; background-color: #ff0000; border-radius: 12px; display: flex; align-items: center; justify-content: center; box-shadow: 0 4px 14px rgba(0,0,0,0.5); transition: transform 0.2s, background-color 0.2s;\">\n        <svg width=\"22\" height=\"22\" viewBox=\"0 0 24 24\" fill=\"#ffffff\" style=\"margin-left: 3px;\">\n          <polygon points=\"5 3 19 12 5 21 5 3\"><\/polygon>\n        <\/svg>\n      <\/div>\n    <\/a>\n\n    <!-- Video Subtitle & Description -->\n    <div style=\"margin-top: 20px; margin-bottom: 22px;\">\n      <div style=\"color: #cbd5e1; font-size: 1.7rem !important; font-weight: 600; line-height: 1.5;\">\n        NVMe-IP DDR Reference Design\n      <\/div>\n      <div style=\"color: #94a3b8; font-size: 1.5rem !important; line-height: 1.5; margin-top: 4px;\">\n        Sustained Data Rate Demo on AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105\n      <\/div>\n    <\/div>\n\n    <!-- Orange CTA Button -->\n    <div>\n      <a href=\"https:\/\/www.youtube.com\/watch?v=Zwk0r-TVuNA\" target=\"_blank\" rel=\"noopener\" style=\"display: inline-flex; align-items: center; justify-content: center; gap: 8px; background: linear-gradient(180deg, #ff8a00 0%, #e56b00 100%); color: #ffffff !important; font-size: 1.6rem !important; font-weight: 700; padding: 12px 30px; border-radius: 5px; text-decoration: none; box-shadow: 0 3px 8px rgba(229, 107, 0, 0.4); border: 1px solid #ff9924; transition: opacity 0.2s;\">\n        <span style=\"font-size: 1.4rem;\">\u25b6<\/span> Watch Demo Video\n      <\/a>\n    <\/div>\n\n  <\/div>\n<\/div>\n\n<!-- Free Evaluation Demo Table -->\n<div style=\"margin: 35px 0;\">\n  <h3 style=\"display: flex; align-items: center; gap: 10px; margin-bottom: 16px;\">\n    <svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" fill=\"none\" stroke=\"#0284c7\" stroke-width=\"2\" stroke-linecap=\"round\" stroke-linejoin=\"round\"><rect x=\"2\" y=\"2\" width=\"20\" height=\"20\" rx=\"2.18\" ry=\"2.18\"><\/rect><line x1=\"7\" y1=\"2\" x2=\"7\" y2=\"22\"><\/line><line x1=\"17\" y1=\"2\" x2=\"17\" y2=\"22\"><\/line><line x1=\"2\" y1=\"12\" x2=\"22\" y2=\"12\"><\/line><line x1=\"2\" y1=\"7\" x2=\"7\" y2=\"7\"><\/line><line x1=\"2\" y1=\"17\" x2=\"7\" y2=\"17\"><\/line><line x1=\"17\" y1=\"17\" x2=\"22\" y2=\"17\"><\/line><line x1=\"17\" y1=\"7\" x2=\"22\" y2=\"7\"><\/line><\/svg>\n    Replicate on Real Hardware: Free Evaluation Bitfile\n  <\/h3>\n  <p style=\"margin-bottom: 20px;\">\n    Engineers can independently replicate the tests from this case study or profile their own target NVMe\u2122 SSD drives on the AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105 board. Select the package that matches your adapter hardware setup:\n  <\/p>\n\n  <div style=\"overflow-x: auto;\">\n    <table style=\"width: 100%; border-collapse: collapse; font-size: 1.7rem; text-align: left; background: #ffffff; border: 1px solid #bae6fd; border-radius: 8px; overflow: hidden;\">\n      <thead>\n        <tr style=\"background: #f0f9ff; border-bottom: 2px solid #bae6fd; color: #0369a1;\">\n          <th style=\"padding: 14px 18px; font-weight: 700;\">Configuration<\/th>\n          <th style=\"padding: 14px 18px; font-weight: 700;\">FPGA Board<\/th>\n          <th style=\"padding: 14px 18px; font-weight: 700;\">Adapter<\/th>\n          <th style=\"padding: 14px 18px; font-weight: 700; text-align: center;\">Download<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr style=\"border-bottom: 1px solid #e2e8f0;\">\n          <td style=\"padding: 16px 18px; font-weight: 600; color: #0f172a;\">KCU105 + AB17<\/td>\n          <td style=\"padding: 16px 18px;\">AMD KCU105<\/td>\n          <td style=\"padding: 16px 18px;\"><span style=\"background: #e0f2fe; color: #0369a1; padding: 4px 10px; border-radius: 4px; font-weight: 600; font-size: 1.5rem;\">AB17-M2FMC<\/span><\/td>\n          <td style=\"padding: 16px 18px; text-align: center;\">\n            <a href=\"https:\/\/dgway.com\/download\/download_form.html?d=NVMeDdrTest_Config_KCU105_AB17.zip\" target=\"_blank\" rel=\"noopener\" style=\"display: inline-block; background-color: #0284c7; color: #ffffff !important; font-weight: 700; padding: 8px 16px; border-radius: 4px; text-decoration: none; font-size: 1.5rem;\">Download \u2193<\/a>\n          <\/td>\n        <\/tr>\n        <tr>\n          <td style=\"padding: 16px 18px; font-weight: 600; color: #0f172a;\">KCU105 + AB18<\/td>\n          <td style=\"padding: 16px 18px;\">AMD KCU105<\/td>\n          <td style=\"padding: 16px 18px;\"><span style=\"background: #e0f2fe; color: #0369a1; padding: 4px 10px; border-radius: 4px; font-weight: 600; font-size: 1.5rem;\">AB18-PCIe\u00aeX16<\/span><\/td>\n          <td style=\"padding: 16px 18px; text-align: center;\">\n            <a href=\"https:\/\/dgway.com\/download\/download_form.html?d=NVMeDdrTest_Config_KCU105_AB18.zip\" target=\"_blank\" rel=\"noopener\" style=\"display: inline-block; background-color: #0284c7; color: #ffffff !important; font-weight: 700; padding: 8px 16px; border-radius: 4px; text-decoration: none; font-size: 1.5rem;\">Download \u2193<\/a>\n          <\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/div>\n\n<!-- CTA Banner -->\n<div class=\"dg-cta-container\">\n  <h3>Ready to Validate Your Sustained Data Logging Solution?<\/h3>\n  <p>\n    Design Gateway provides complete reference designs, IP cores, and engineering support for high-throughput storage applications on AMD Kintex\u2122 UltraScale\u2122 platforms.\n  <\/p>\n  <div class=\"dg-btn-group\">\n    <a href=\"https:\/\/dgway.com\/contact.html\" class=\"dg-btn-primary\" target=\"_blank\" rel=\"noopener\">Request Evaluation Demo<\/a>\n    <a href=\"https:\/\/www.dgway.com\/NVMe-IP_X_E.html\" class=\"dg-btn-outline\" target=\"_blank\" rel=\"noopener\">Explore NVMe\u2122-IP Core<\/a>\n  <\/div>\n<\/div>\n\n<!-- End of .dg-blog-wrapper -->\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Case Study Overview: In mission-critical edge recording and continuous instrumentation, relying on peak SSD datasheets often results in catastrophic data loss. This case study demonstrates how empirical testing on the AMD Kintex\u2122 UltraScale\u2122 FPGA KCU105 Evaluation Kit using Design Gateway\u2019s NVMe\u2122 SSD Characteristic Test Platform validates sustained read\/write throughput and precisely identifies external DDR buffer requirements. Modern high-speed data acquisition&#46;&#46;&#46;<\/p>\n","protected":false},"author":1,"featured_media":3933,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[13,8,6,19,12],"tags":[127,40,237,129],"class_list":["post-3922","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-accelerator-systems-webinar","category-fpga-technology","category-storage","category-vertical-market","category-webinar","tag-design-gateway","tag-fpga","tag-fpga-ip-core","tag-high-speed-data-transfer"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/3922","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=3922"}],"version-history":[{"count":25,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/3922\/revisions"}],"predecessor-version":[{"id":3953,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/3922\/revisions\/3953"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/3933"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=3922"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=3922"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=3922"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}