{"id":422,"date":"2022-04-20T09:20:13","date_gmt":"2022-04-20T02:20:13","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=422"},"modified":"2022-04-20T09:22:44","modified_gmt":"2022-04-20T02:22:44","slug":"002-using-multiple-ddr-banks","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2022\/04\/20\/002-using-multiple-ddr-banks\/","title":{"rendered":"#002 Using Multiple DDR Banks"},"content":{"rendered":"\n

Based on Xilinx\u2019s VitisTM<\/sup> Application Acceleration Development Flow Tutorial:<\/p>\n\n\n\n

https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/2021.2\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks<\/a><\/p>\n\n\n\n

By default, the data transfer between the Kernel and the DDR is accomplished by using single DDR. In some applications, transferring large amount of data between global memory (DDR) and FPGA can be a cause of performance dropped. Using multiple DDR banks can be one of the solutions. Therefore, this tutorial illustrates you how to map kernel ports to multiple DDR banks.<\/p>\n\n\n\n

Overviews<\/strong><\/p>\n\n\n\n

In this tutorial, it uses a simple vector addition, called \u2018vadd\u2019. The \u2018vadd\u2019 kernel is reading data from \u2018in1\u2019 and \u2018in2\u2019 and the result is \u2018out\u2019. The basic behavior of Vitis core development is to use only a single DDR bank to exchange data between kernel and global memory. In this case, all the data access of port \u2018in1\u2019, \u2018in2\u2019 and \u2018out\u2019 of \u2018vadd\u2019 kernel come from the default DDR bank only, as shown in picture below.<\/p>\n\n\n\n

\"\"
Thanks for the pic from https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/2021.2\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks<\/a><\/figcaption><\/figure><\/div>\n\n\n\n

The picture below demonstrates a plan to reduce the load of access data by using multiple DDR which will carry out in this tutorial later.<\/p>\n\n\n\n

\"\"
Thanks for the pic from https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/2021.2\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks<\/a><\/figcaption><\/figure><\/div>\n\n\n\n

Step by step to run on TKAS<\/strong><\/p>\n\n\n\n

Using set environment and old folder from last issue. Then, navigate to .\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks\/reference-files<\/p>\n\n\n\n

Changing configuration for Alveo U250 card<\/strong><\/p>\n\n\n\n

File makefile<\/p>\n\n\n\n

Line 4 | PLATFORM := xilinx_u250_gen3x16_xdma_3_1_202020_1<\/mark><\/p>\n\n\n\n

Save makefile and close.<\/p>\n\n\n\n

Build<\/strong> & Check<\/strong><\/p>\n\n\n\n

Execute the command below in order to see the default behavior of Vitis core development tool<\/p>\n\n\n\n

make all<\/mark><\/em><\/p>\n\n\n\n

After execute command, user would see the console indicate the default behavior as picture below<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

To ensure the automatically mapping of Vitis development core, user can be used option \u2018check\u2019 when execute \u2018make\u2019 command as below.<\/p>\n\n\n\n

make check<\/mark><\/em><\/p>\n\n\n\n

After the simulation complete, the report of memory transfer is generated as shown below.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

As you can see, all data transfer is done by using DDR bank 1 only. User can view it as graphic by using command below<\/p>\n\n\n\n

vitis_analyzer vadd.hw_emu.xclbin<\/mark><\/em><\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

From now on, this is steps to use multiple DDR in order to reduce bottleneck due to using single DDR data transfer.<\/p>\n\n\n\n

Set v++ Linker options<\/strong><\/p>\n\n\n\n

navigate to .\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks\/reference-files<\/p>\n\n\n\n

Open the makefile comment line 18 and uncomment line 19 in order to use file connectivity.cfg instead of using default behavior of Vitis development core relevant to mapping DDR bank, as shown in picture below.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

The connectivity.cfg file is shown below.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

sp = <kernel_cu_name>.<kernel_arg>:<sptag>
sp : the option to allow user to map kernel port to a specific global memory banks.
<kernel_cu_name> : The compute unit (CU) based on the kernel name followed by \u2018_\u2019 and index.
<kernel_arg> : The function argument of the CU, for this tutorial is argument as found in \u2018vadd.cpp\u2019 file
<sptag> : Represents a memory resource available on the target platform.<\/p>\n\n\n\n

Build<\/strong> & Check<\/strong><\/p>\n\n\n\n

Execute the command below in order to perform multiple DDR banks<\/p>\n\n\n\n

make all<\/mark><\/em><\/p>\n\n\n\n

After execute command, user would see the console indicate the default behavior as picture below<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

To confirm using multiple DDR by using makefile with option check as shown below<\/p>\n\n\n\n

make check<\/mark><\/em><\/p>\n\n\n\n

After test is completed, the message shows as below<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Furthermore, to view a graphic of multiple DDR bank by using below command<\/p>\n\n\n\n

vitis_analyzer vadd.hw_emu.xclbin<\/mark><\/em><\/p>\n\n\n\n

<\/p>\n\n\n\n

\"\"<\/figure>\n","protected":false},"excerpt":{"rendered":"

Based on Xilinx\u2019s VitisTM Application Acceleration Development Flow Tutorial: https:\/\/github.com\/Xilinx\/Vitis-Tutorials\/tree\/2021.2\/Hardware_Acceleration\/Feature_Tutorials\/04-mult-ddr-banks By default, the data transfer between the Kernel and the DDR is accomplished by using single DDR. In some applications, transferring large amount of data between global memory (DDR) and FPGA can be a cause of performance dropped. Using multiple DDR banks can be one of the solutions. Therefore, this...<\/p>\n","protected":false},"author":1,"featured_media":424,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[11],"tags":[],"class_list":["post-422","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-accelerated-computing-tutorial"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/422","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=422"}],"version-history":[{"count":3,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/422\/revisions"}],"predecessor-version":[{"id":438,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/422\/revisions\/438"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/424"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=422"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=422"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=422"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}