{"id":463,"date":"2022-05-18T19:30:00","date_gmt":"2022-05-18T12:30:00","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=463"},"modified":"2022-05-19T07:39:09","modified_gmt":"2022-05-19T00:39:09","slug":"003-from-rtl-ip-core-to-rtl-kernel-with-host-application-demo","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2022\/05\/18\/003-from-rtl-ip-core-to-rtl-kernel-with-host-application-demo\/","title":{"rendered":"#003 \u2013 From RTL IP core to RTL Kernel with Host Application demo"},"content":{"rendered":"\n

For Turnkey Accelerator System (TKAS-D2101) with Alveo U250 Card and Xilinx Vitis\u2122 Unified Software Platform 2021.1<\/strong><\/p>\n\n\n\n

Based on Xilinx\u2019s Vitis\u2122 Application Acceleration Development Flow Tutorials: bottom_up_rtl_kernel<\/a><\/p>\n\n\n\n

This tutorial introduces a bottom-up Vitis-based RTL kernel construct and wrap-up process, as well as the host-kernel interaction with Xilinx Runtime library (XRT)<\/a>. All the steps in this tutorial use the command-line interface, except those needed to view waveform or system diagram.
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This tutorial uses an example design to illustrate the relevant concept and steps. The following image shows the block diagram of this design. It is a simple AES accelerator design and comprises two kernels, krnl_aes and krnl_cbc. The krnl_aes kernel is the core AES computation core with AXI streams slave and master ports. The krnl_cbc kernel handles the host-kernel data exchange, and the implementation of AES-ECB and AES-CBD modes along with the krnl_aes module.<\/p>\n\n\n\n

Step by Step to run on TKAS-D2101<\/strong><\/p>\n\n\n\n

Set enviroment<\/h1>\n\n\n\n

source \/tools\/Xilinx\/Vitis\/2021.1\/settings64.sh
source \/opt\/xilinx\/xrt\/setup.sh<\/code><\/p>\n\n\n\n

Goto working folder from example #001<\/h1>\n\n\n\n
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Additional requirements for Ubuntu<\/strong><\/p>\n\n\n\n

sudo apt install libssl-dev<\/code><\/p>\n\n\n\n

AES HDL(Verilog) & Simulation<\/strong><\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Run make script to simulate<\/strong><\/p>\n\n\n\n

cd ~\/aes
make runsim<\/p>\n\n\n\n

Simulation result<\/strong><\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

The simulation is executed with 256 input words (128-bit) along with pre-defined KEY. You can modified the simulation options in the ~\/aes\/runsim_aes_xsim.sh file. After simulation finishes, a waveform dump file called work.tb_aes.wdb <\/strong>is generated, in which you can view the interface waveform.<\/p>\n\n\n\n

Open WDB wavform dump file from console<\/strong><\/p>\n\n\n\n

Create TCL script file name “open_waveform.tcl” with content below<\/p>\n\n\n\n

current_fileset<\/code>
open_wave_database work.tb_aes.wdb<\/code><\/p>\n\n\n\n

Run vivado tcl script to open WDB waveform<\/p>\n\n\n\n

vivado -source open_waveform.tcl<\/code><\/p>\n\n\n\n

Waveform windows<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Create RTL module and pack into Vivado\u00ae IP and Vitis Kernel (XO) file<\/strong><\/p>\n\n\n\n