{"id":495,"date":"2022-07-29T12:29:55","date_gmt":"2022-07-29T05:29:55","guid":{"rendered":"https:\/\/dgway.com\/blog_E\/?p=495"},"modified":"2022-08-15T23:19:32","modified_gmt":"2022-08-15T16:19:32","slug":"aes-pure-logic-vs","status":"publish","type":"post","link":"https:\/\/dgway.com\/blog_E\/2022\/07\/29\/aes-pure-logic-vs\/","title":{"rendered":"AES: HW(RTL) vs SW(HLS) comparison"},"content":{"rendered":"\n

As in the previous article that we talked about AES, you know about how AES works, type of AES and the benefits of using it. This article shows the comparison between using AES Hardware development which is pure logic or Register-Transfer-Level (RTL) and AES Software development on ALVEO card, which is based on High-Level-Synthesis (HLS) Language, in 3 aspects. Flexibility of ip core, base development and size of ip core. <\/p>\n\n\n\n

Flexibility of AES Core<\/strong><\/p>\n\n\n\n

Most AES RTL IP cores are designed and optimized for a specific purpose. For example, the AES256 RTL IP core is designed to support 256 bits key only, meanwhile the AES IP Core running on ALVEO card can be customized to support 128-bit, 192-bit and 256-bit keys. <\/p>\n\n\n\n

Implementation: RTL vs HLS<\/strong><\/p>\n\n\n\n

RTL or pure hardware logic is a traditional way to implement logic on FPGA. However, as the growth of the market has pushed manufacturers to improve the methodology to implement FPGA from hardware perspective to software aspect. As a result, AES on ALVEO card is easy to use and friendly to software engineers who just started to work on FPGA. Furthermore, new users do not have to worry about FPGA settings because the software already handles those parameters.<\/p>\n\n\n\n

In addition, software engineers would be familiar with the language used in developing projects due to it being based on C\/C++ and script languages. Therefore, it helps reduce time of development.

Anyway, RTL implemetation can achieve higher performance than HLS.<\/p>\n\n\n\n

Resource usage \/ Size of IP core<\/strong><\/p>\n\n\n\n

In general, the pure logic ip core is smaller than the ip core generated from the manufacturer, it is also in this case. For example, The AES pure logic from Design Gateway has 128 bit inputs, the same as the AES in the previous article. Even Though, the architecture of the FPGA, a Zynq-Ultrascale+, from pure logic AES of Design Gateway is old. It shows a smaller size than the new architecture, the Alveo card. If the AES pure logic is compiled on the new architecture. It can be smaller than what it is on the old architecture. <\/p>\n\n\n

\n
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Size of IP of pure logic<\/figcaption><\/figure>\n<\/div>\n\n
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Size of IP of Software Dev<\/figcaption><\/figure>\n<\/div>\n\n\n

Summary<\/strong><\/p>\n\n\n\n

The benefit of using AES over Alveo card is the various types of configuration of AES on Alveocard. Furthermore, the time spent on the development phase might be shorter than developing projects on pure logic design due to the languages used in development. However, the pure logic has its own strong point which is the size. Therefore, users can add more features due to spare spaces from AES. The table below is shown the comparison between AES sw and AES hw from design gateway.<\/p>\n\n\n

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\"\"<\/figure>\n<\/div>\n\n\n

if you are interested in AES hw from design gateway. please visit https:\/\/dgway.com\/ASIP_E.html<\/p>\n","protected":false},"excerpt":{"rendered":"

As in the previous article that we talked about AES, you know about how AES works, type of AES and the benefits of using it. This article shows the comparison between using AES Hardware development which is pure logic or Register-Transfer-Level (RTL) and AES Software development on ALVEO card, which is based on High-Level-Synthesis (HLS) Language, in 3 aspects. Flexibility...<\/p>\n","protected":false},"author":1,"featured_media":503,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[5],"tags":[],"class_list":["post-495","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-security"],"_links":{"self":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/495","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/comments?post=495"}],"version-history":[{"count":5,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/495\/revisions"}],"predecessor-version":[{"id":512,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/posts\/495\/revisions\/512"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media\/503"}],"wp:attachment":[{"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/media?parent=495"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/categories?post=495"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgway.com\/blog_E\/wp-json\/wp\/v2\/tags?post=495"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}