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1 Introduction
2 Hardware Overview
2.1 LAxi2Reg
2.2 AsyncAxiReg
2.3 UserReg
2.3.1 Encryption key setting
2.3.2 Tweakable key setting
2.3.3 parameter setting
2.3.4 Encryption
2.3.5 Decryption
3 CPU Firmware
3.1 Set encryption key
3.2 Set tweakable key
3.3 Set encryption/decryption IV
3.4 Show Data Memory
3.5 Fill Plain Data Memory
3.6 Encrypt
3.7 Fill Cipher Data Memory
3.8 Decrypt
4 Revision History
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AES256XTS IP Reference Design