Features Applications Reference design General Description Functional Description MAC Layer FCS Processor - Insertion Frame Processor - Encoder The Controller - Tx FCS Processor - Checker Frame Processor - Decoder The Controller - Rx PCS layer Tx PCS Rx PCS RS-FEC layer RSFEC Encoder RSFEC Decoder User Logic 25G Ethernet PCS/PMA (25GBASE-R) 8 25G Ethernet PCS/PMA (25GBASE-R) Core I/O Signals Timing Diagram. IP Initialization Transmit Interface Receive Interface IP Status Interface for RS-FEC Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top