1 Introduction 2 Hardware overview 2.1 25G Ethernet PMA (25G BASE-R) 2.2 XXVGMACRSFEC-IP 2.3 PacketGen 2.4 EMAC Timer 2.5 CPU and Peripherals 2.5.1 AsyncAxiReg 2.5.2 UserReg 3 CPU Firmware on FPGA 3.1 Reset EMAC and Transceiver 3.2 Loopback Transfer Test 3.3 Bit Error Rate Test 3.4 Function list in User application 4 Revision History Return to Top