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1 Introduction
2 Hardware overview
2.1 Xilinx Transceiver (PMA for 10GBASE-R)
2.2 LL10GEMAC-IP
2.3 PMARstCtrl
2.4 PacketGen
2.5 Timer
2.6 CPU and Peripherals
2.6.1 AsyncAxiReg
2.6.2 UserReg
3 CPU Firmware Sequence
3.1 Change Loopback Mode
3.2 Run Loopback Test
3.3 Function list in User application
4 Revision History
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LL10GEMAC-IP reference design