1 Introduction 2 DG LL-IP kernel (Hardware) 2.1 Xilinx Transceiver (PMA for 10GBASE-R) 2.2 LL10GEMAC 2.3 PMARstCtrl 2.4 LL10GEMACTxIF and LL10GEMACRxIF 2.5 UDP10GRx16SS 2.5.1 TxEMACMux4to1 2.5.2 UDP10GRxIP 2.5.3 UDPRx16SS2AXI4 2.6 TOE10GLL32SS 2.6.1 TxEMACMux4to1 and TxEMACMux8to1 2.6.2 TOE10GLLIP 2.6.3 TOEAsyncAXICmd 2.6.4 TOETx32SSAXI4 2.6.5 TOERx32SS2AXI4 2.7 LAxi2Reg 2.7.1 SAXIReg 2.7.2 UserReg 3 Other kernels in AAT (hardware) 3.1 LineHandler kernel 3.2 OrderEntry Kernel 4 The host software 4.1 Driver Layer 4.1.1 DG LL-IP Driver 4.1.2 Line Handler Driver 4.1.3 Order Entry Driver 4.2 Shell Object 4.2.1 DG LL-IP Shell 4.2.2 Line Handler Shell 4.2.3 Order Entry Shell 4.2.4 AAT Shell 4.3 Application Layer 4.3.1 “xlnx_aath” 4.3.2 “xlnx_aatcpp” 4.3.3 “maincpp” 4.4 CMakeList file 4.4.1 Modified CMakeLists file 4.4.2 Added CMakeLists files 5 DG LL-IP modification 6 Revision History Return to Top