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1 Introduction
2 Hardware overview
2.1 Xilinx Transceiver (PMA for 10GBASE-R)
2.2 LL10GEMAC
2.3 PMARstCtrl
2.4 TOE10GLL
2.5 TxEMACMux8to1 and TxEMACMux4to1
2.5.1 TxEMACMux8to1
2.5.2 TxEMACMux4to1
2.6 CPU and Peripherals
2.6.1 AsyncAxiReg
2.6.2 UserReg
3 CPU Firmware (FPGA)
3.1 Display parameters
3.2 Reset parameters
3.3 Half Duplex Test
3.4 Full duplex test
3.5 Function list in User application
4 Test Software on PC
4.1 tcpdatatest for half duplex test
4.2 tcp_client_txrx_single for full duplex test
5 Revision History
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TOE10GLL-IP (Cut-through) 32-session reference design