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1 Introduction 2 Hardware overview 2.1 Xilinx Transceiver (PMA for 10GBASE-R) 2.2 LL10GEMAC 2.3 PMARstCtrl 2.4 TOE10GLL 2.5 CPU and Peripherals 2.5.1 AsyncAxiReg 2.5.2 UserReg 2.6 Timer 3 CPU Firmware (FPGA) 3.1 Display parameters 3.2 Reset parameters 3.3 Send data test 3.4 Receive data test 3.5 Full duplex test 3.6 Function list in User application 4 Test Software on PC 4.1 “tcpdatatest” for half duplex test 4.2 “tcp_client_txrx_40G” for full duplex test 5 Revision History Return to Top

TOE10GLL-IP (Cut-through mode) reference design