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Features Applications General Description Functional Description NVMe NVMe Host Controller Command Parameter Data Buffer (256KB RAM) NVMe Data Controller PCIe PCIe Config PCIe Adapter Async Control User Logic PCIe Hard IP from Altera (GTS AXI Streaming IP for PCIe) Core I/O Signals Timing Diagram. Initialization Control Interface of dgIF typeS Data Interface of dgIF typeS IdenCtrl/IdenName Shutdown SMART Secure Erase Flush Error Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top

NVMe IP Core for AG5 Datasheet