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Features

· NVMe host controller for access one NVMe SSD without CPU and external memory

· Support two users to access one SSD simultaneously

· Simple user interfaces by dgIF typeS

· Include two 256-Kbyte RAMs for two users

· Command support:

· User#0 (Main user): Identify, Shutdown, Write, Read, SMART, and Flush

· User#1 (Sub user): Write and Read

· Supported NVMe device

· Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)

· MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)

· MDTS (Maximum Data Transfer Size): At least 5 (128 Kbyte) or 0 (no limitation)

· LBA unit: 512 bytes or 4096 bytes

· Support multiple queues

· User clock frequency must be more than or equal to PCIe clock (250MHz for Gen3)

· Operating with Integrated Block for PCI Express from Xilinx by using 4-lane PCIe Gen3 (128-bit bus interface)

· One muNVMe IP connects to one NVMe SSD directly

· Available reference design:

· Two-user demo on KCU116 and ZCU106

· 2-ch RAID0 demo on ZCU106

· Customized service for following features

· Additional NVMe commands

· Increase user channel

Table 1: Example Implementation Statistics

Family

Example Device

Fmax

(MHz)

CLB Regs

CLB LUTs

CLB¹

IOB

BRAM

Tile

URAM

GTX

Design

Tools

Kintex-Ultrascale+

XCKU5P-FFVB676-2E

400

6843

3974

956

Vivado2019.1

Zynq-Ultrascale+

XCZU7EV-FFVC1156-2E

400

6843

3970

973

Vivado2019.1

Notes:

1) Actual logic resource dependent on percentage of unrelated logic

Applications

Figure 1: muNVMe IP Application

muNVMe IP Core integrated with Integrated Block for PCI Express (PCIe hard IP) from Xilinx is ideal to access one NVMe SSD without CPU and external memory such as DDR. In Accordance with two-user interface, two users are allowed to access one NVMe SSD parallelly. Thus, this solution fits the application which needs to record data to NVMe SSD and read some data in different region at the same time. When an Ethernet IP Core is connected to muNVMe IP, the remote host concept can be adapted for transferring and monitoring data progress across Ethernet network as shown in Figure 1.

General Description

Figure 2: muNVMe IP Block Diagram

muNVMe IP implements as host controller to access NVMe SSD following NVM express standard. Physical interface of NVMe SSD is PCIe. The low-layer hardware is implemented by using Integrated Block for PCI Express (PCIe hard IP) from Xilinx.

muNVMe IP supports six NVMe commands, i.e., Identify, Shutdown, Write, Read, SMART, and Flush command with two user interfaces - User#0 I/F and User#1 I/F. User#0 I/F is the interface of NVM#0 module inside muNVMeIP while User#1 I/F is the interface of NVM#1 module. All six commands are supported by NVM#0 (Main) while NVM#1 (Sub) supports only Write and Read command.

For operating each command, User#0 I/F and User#1 I/F consists of two interface groups. First is Control interface for transferring command and the parameters. Another is Data interface for transferring data when the command must have the data transferring. The Control interface and Data interface for Write/Read command use dgIF typeS format. Control interface of dgIF typeS consists of start address and transfer length with asserting the request signal while Data interface of dgIF typeS is the FIFO interface.

SMART and Flush command require the specific interface, called Custom command interface, which consists of Ctm I/F for control path and Ctm RAM I/F for data path. Furthermore, Identify command has its own data interface, named Iden RAM I/F, as shown in Figure 2. All of these specific interfaces are integrated only in User#0 I/F.

Due to two user interfaces, while Write or Read command is operating in NVM#1, some commands can be operating parallelly in NVM#0, i.e., Identify, Write, Read, SMART, and Flush. However, there is one limitation about the parallel operation. Shutdown command must be executed after NVM#0 and NVM#1 return back to be idle. Thus, NVM#0 must not be requested for Shutdown command while NVM#1 operates Write/Read command.

During initialization process or running some commands, error signal may be asserted by muNVMe IP if some abnormal conditions are found. The IP includes the error status to check the more details of error condition. To recover error status, muNVMe IP and SSD must be reset.

There is one limitation about clock frequency of user logic. Transmit packet to PCIe hard IP must be sent continuously until end of packet. Therefore, data must be valid every clock between start of packet and end of packet. To support this feature, user logic clock frequency must be more than or equal to PCIe clock frequency (250 MHz for PCIe Gen3) to have the bandwidth of transmit logic higher than or equal to PCIe hard IP bandwidth.

The reference designs on FPGA evaluation boards are available for evaluation before purchasing.

Functional Description

Figure 3: Operation Flow of muNVMe IP

The operation flow of muNVMe IP is divided into three phases, i.e., Intialization, Command operation, and No operation as shown in Figure 3. Firstly, the Initialization phase is handled by User#0 I/F. In this phase, User#1 I/F merely waits until the end of Initialization. The Initialization step includes

1) NVM#0 waits until PCIe is ready by monitoring Linkup status from PCIe IP core.

2) NVM#0 begins the initialization process by setup PCIe registers and NVMe registers. If some errors are detected during setup process, NVM#0 changes the IP to the Inactive state.

After that, both user interfaces are idle and ready to receive command from user. The command can be requested to User#0 I/F and User#1 I/F parallelly except Shutdown command. All users must be idle before Shutdown command is requested through User#0 I/F. After the shutdown is completed, NVM#0 and NVM#1 change to the Inactive state.

More details of each command operation flow in Command operation phase of NVM#0 are shown in Figure 4.

Figure 4: Command Operation Flow of NVM#0, controlled by User#0 I/F

1) The 1^st command from user must be Identify command (U0Cmd=000b) to update LBASize (disk capacity) and LBAMode (LBA unit=512 bytes or 4 Kbytes).

2) The last command before power down the system must be Shutdown command (U0Cmd=001b). This command is recommended to guarantee SSD powered down in a good sequence. Without Shutdown command, Write data in SSD cannot be guaranteed. After Shutdown command is done, muNVMe IP and SSD enter to the Inactive state and do not receive any commands until the IP is reset.

3) When Write command is requested to NVM#0 (U0Cmd=010b), the maximum data size for one command is 128 Kbytes. If total length from user is more than 128 Kbytes, repeat step 3a) – 3b) for many times.

a) The IP waits until Write data, sent by user, is enough for one command (transfer size of one command in muNVMe IP is 128 Kbytes, except the last loop which could be less than 128 Kbytes).

b) The IP sends Write command to SSD and then waits until the status is returned from SSD. NVM#0 status changes to the Idle state when total data is completely transferred. Otherwise, NVM#0 goes back to step 3a) to send the next Write command.

4) Similar to Write command, Read command (U0Cmd=011b) must be sent by NVM#0 to the SSD many times when total length from user is more than 128 Kbytes. As the result, step 4a) – 4b) are repeated many times.

a) The IP waits until free space of Data Buffer#0 in muNVMe IP is enough for one command. If remaining transfer size is equal to zero, the IP skips to step 4c).

b) The IP sends Read command to SSD. After that, goes back to step 4a) to check the remaining transfer size and the free space of Data Buffer#0.

c) IP waits until all data are completely transferred from NVM#0 Data Buffer to UserLogic and then changes NVM#0 status back to the Idle state. Therefore, Data Buffer of NVM#0 is empty after Read command is done.

5) For SMART command (U0Cmd=100b), 512-byte data is returned after the operation is done.

a) IP sends Get Log Page command to read SMART/Health information from SSD.

b) 512-byte data is returned from the SSD. The IP forwards the data through Custom command RAM interface (CtmRamAddr=0x000 – 0x01F).

6) For Flush command (U0Cmd=110b), there is no data transferring during the operation.

a) IP sends Flush command to SSD.

b) IP waits until SSD returns status to complete the operation.

For Write command (U1Cmd=010b) and Read command (U1Cmd=011b) of NVM#1, the operation flow is completely the same as Write and Read command of NVM#0 by using sepearted operation core and Data Buffer of NVM#1.

To design NVMe host controller, muNVMe IP implements two protocols, i.e., NVMe protocol for interfacing with user and PCIe protocol for interfacing with PCIe hard IP. Therefore, the hardware inside muNVMe-IP is divided to NVMe block and PCIe block. The details of the hardware inside muNVMe IP are described as follows.

NVMe

muNVMe IP supports six commands, i.e., Identify, Write, Read, SMART, Flush, and Shutdown command which can split in two command types, i.e., Admin command and NVM command. muNVMe IP supports three Admin commands, i.e., Identify, Shutdown, and SMART command and supports three NVM commands, i.e., Write, Read, and Flush command. After the command operation is done, the status returned from the SSD is latched to AdmCompStatus signal when running Admin command or U0-U1IOCompStatus signal when running NVM command.

The parameters of Write or Read command are set by Control interface of dgIF typeS while the parameters of SMART or Flush command are set by CtmSubm of Ctm interface. Data interface for Write or Read command is transferred by FIFO interface, a part of dgIF typeS, which is finally connected with 256-Kbyte buffers inside the NVM#0/NVM#1. The data interface of other commands has its own interface, i.e., Identify RAM for Identify command and Custom RAM for SMART command.

For implement NVMe protocol, both NVM#0 and NVM#1 are designed to have four NVMe submodules, i.e., NVMe Host Controller, Command Parameter, Data Buffer, and NVMe Data Controller. However, submodule features and complexity between NVM#0 and NVM#1 are not exactly identical because of different user command support. The details of each submodule are described as follows.

· NVMe Host Controller

NVMe Host Controller is the main controller of each NVM. On the other word, it is the main controllers of muNVMe IP. The module operation is split into two phases. First is the initialization phase which is once run after the system is boot up for setting NVMe register inside the SSD. The initialization is operated only in NVMe Host Controller#0 as described early in Figure 3. After finishing the initialization phase, the next phase is the command operation phase. The order of transmitted and received packet in each user interface is controlled by its NVMe Host Controller.

To operate the command, the parameters of each command are prepared in Command Parameter and then forwarded to AsyncCtrl. After finishing the command, the status packet returned from SSD is monitored by NVMe Host Controller to check if no error is found. When the command needs to transfer data such as Write, Read, SMART, and Identify command, NVMe Host Controller must also handle with NVMe data controller.

· Command Parameter

This module is designed to prepare command packet for SSD and also decode status packet returned from SSD.

Typically, the command consists of 16 Dwords (1 Dword = 32-bit). When running Identify, Shutdown, Write, or Read command, all 16 Dwords are created by Command Parameter, following the user inputs on dgIF typeS. When running SMART and Flush command, all 16 Dwords are directly loaded via CtmSubmDW0-CtmSubmDW15 of Ctm interface.

· Data Buffer

256-Kbyte simple dual port RAM is implemented by URAM to be data buffer of each user interface. The buffer stores data transferred between UserLogic and SSD during Write and Read command operation.

· NVMe Data Controller

This module is operated when the command must transfer the data, i.e., Identify, SMART, Write, and Read command. There are three data interfaces for transferring with the SSD, i.e., FIFO interface with 256-Kbyte buffer when running Write or Read command, Custom command RAM interface when running SMART command, or Identify RAM interface when running Identify command.

When running Write or Read command, the address of the Data Buffer is controlled by NVMe Data controller.

PCIe

The PCIe standard is the outstanding low-layer protocol for very high speed application. The NVMe standard is the protocol which is run over PCIe protocol. In the initialization process, NVMe layer is setup after finishing PCIe layer setup. Two modules are designed to support PCIe protocol, i.e., PCIe Controller and AsyncCtrl. More details of each module are described as follows.

· PCIe Controller

During initialization process, PCIe Controller sets up PCIe environment of SSD via CFG interface. After that, PCIe packet is created or decoded via 128-bit Tx/Rx AXI4-Stream. The command packet and data packet from NVMe module are converted to be PCIe packet by PCIe Controller. On the other hand, the received PCIe packet is decoded and converted to be NVMe packet for NVMe module by this module. When NVM#0 and NVM#1 operate command parallelly, PCIe controller manages to create or decode PCIe packet to/from the right NVM interface.

· AsyncCtrl

AsyncCtrl includes asynchronous registers and buffers to support clock-domain crossing. Most logics in muNVMe IP run on user clock domain while PCIe hard IP runs on PCIe clock domain. AXI4-stream interface of PCIe hard IP must transfer data of each packet continuously, so the user bandwidth must be greater than or equal to PCIe bandwidth by running at higher or the same clock frequency of PCIe clock.

UserLogic

This module could be designed by using small state machine to send the commands with assigning the parameters for each command. For Write/Read command, the command parameters are address and transfer size. Data interface for Write/Read command can directly connect to FIFO while data output from SMART and Identify command can directly connect to simple dual port RAM. RAM size depends on the data size transferring in each command, but data width of all commands is 128-bit. Data size of Identify command is 8-Kbyte while data size of SMART command is 512-byte.

Integrated Block for PCI Express

Integrated Block for PCI Express is the hard IP provided by Xilinx for some Xilinx FPGAs. The maximum number of SSDs connecting to one FPGA device is limited by the number of PCIe hard IPs in FPGA device. By using muNVMe IP, one PCIe hard IP can connect to one NVMe SSD. More details of PCIe hard IP are described in following document.

PG213: UltraScale+ Devices Integrated Block for PCI Express

Figure 5: Integrated Block for PCI Express (UltraScale+)

Core I/O Signals

Descriptions of all I/O signals are provided in Table 2 - Table 3.

Table 2: User logic I/O Signals (Synchronous to Clk signal)

Signal	Dir	Description
Control I/F of dgIF typeS
RstB	In	Synchronous reset signal. Active low. De-assert to ‘1’ when Clk signal is stable.
Clk	In	System clock for running muNVMe IP. The frequency must be more than or equal to PCIeClk which is output from PCIe hard IP (250 MHz for PCIe Gen3).
U0Cmd[2:0]	In	User Command of User#0 I/F. Valid when U0Req=’1’. “000”: Identify, “001”: Shutdown, “010”: Write SSD, “011”: Read SSD, “100”: SMART, “110”: Flush, Others: Reserved
U1Cmd[2:0]	In	User Command of User#1 I/F. Valid when U1Req=’1’. “010”: Write SSD, “011”: Read SSD, Others: Reserved
U0Addr[47:0]	In	Start address of User#0 I/F to write/read SSD in 512-byte unit. Valid when U0Req=’1’. In case LBA unit = 4 Kbyte, U0Addr[2:0] must be always set to “000” to align 4-Kbyte unit. In case LBA unit = 512 byte, it is recommended to set U0Addr[2:0]=”000” to align 4-Kbyte size (SSD page size). Write/Read performance of most SSDs is reduced when start address is not aligned to page size.
U1Addr[47:0]	In	Description is the same as U0Addr by referring to signal and module of User#1 I/F.
U0Len[47:0]	In	Total transfer size to write/read SSD in 512-byte unit. Valid from 1 to (LBASize-U0Addr). In case LBA unit = 4 Kbyte, U0Len[2:0] must be always set to “000” to align 4-Kbyte unit. Valid when U0Req=’1’.
U1Len[47:0]	In	Description is the same as U0Len by referring to signal and module of User#1 I/F.
U0Req	In	Assert to ‘1’ to send the new command request and de-assert to ‘0’ after IP starts the operation by asserting U0Busy to ‘1’. This signal can be asserted when NVM#0 is Idle (U0Busy=’0’). Command parameters (U0Cmd, U0Addr, U0Len, and CtmSubmDW0-DW15) must be valid and stable during U0Req=’1’. U0Addr and U0Len are inputs for Write/Read command while CtmSubmDW0-DW15 are inputs for SMART/Flush command.
U1Req	In	Assert to ‘1’ to send the new command request and de-assert to ‘0’ after IP starts the operation by asserting U1Busy to ‘1’. This signal can be asserted when NVM#1 is Idle (U1Busy=’0’). Command parameters (U1Cmd, U1Addr, and U1Len) must be valid and stable during U1Req=’1’.
U0Busy	Out	Asserted to ‘1’ when NVM#0 is busy (operate command of User#0 I/F). New request must not be sent (U0Req to ‘1’) when User#0 is busy.
U1Busy	Out	Description is the same as U0Busy by referring to signal and module of NVM#1.
LBASize[47:0]	Out	Total capacity of SSD in 512-byte unit. Default value is 0. This value is valid after finishing Identify command.
LBAMode	Out	LBA unit size of SSD (‘0’: 512 bytes, ‘1’: 4 Kbytes). Default value is 0. This value is valid after finishing Identify command.
U0Error	Out	Error flag. Asserted to ‘1’ when U0ErrorType is not equal to 0. The flag can be cleared by asserting RstB to ‘0’.
U1Error	Out	Description is the same as U0Error by referring to signal and module of NVM#1.

Signal	Dir	Description
Control I/F of dgIF typeS
U0ErrorType[31:0]	Out	[0] – Error when PCIe class code is not correct. [1] – Error from CAP (Controller capabilities) register which may be caused from - MPSMIN (Memory Page Size Minimum) is not equal to 0. - NVM command set flag (bit 37 of CAP register) is not set to 1. - DSTRD (Doorbell Stride) is not 0. - MQES (Maximum Queue Entries Supported) is more than or equal to 7. More details of each register can be checked from NVMeCAPReg signal. [2] – Error when Admin completion entry is not received until timeout. [3] – Error when status register in Admin completion entry is not 0 or phase tag/command ID is invalid. Please see more details from AdmCompStatus signal. [4] – Error when IO completion entry of NVM#0 is not received until timeout. [5] – Error when status register in IO completion entry of NVM#0 is not 0 or phase tag is invalid. Please see more details from U0IOCompStatus signal. [6] – Error when Completion TLP packet size is not correct. [7] – Error when PCIe hard IP detects Error correction code (ECC) error from the internal buffer. [8] – Error from Unsupported Request (UR) flag in Completion TLP packet. [9] – Error from Completer Abort (CA) flag in Completion TLP packet. [15:10] – Reserved [16] – Error from unsupport LBA unit (LBA unit is not equal to 512 bytes or 4 Kbytes) [17] – Error when SSD does not support multiple queues. [31:18] – Reserved Note: Timeout period of bit[2]/[4] is set from TimeOutSet input.
U1ErrorType[31:0]	Out	[3:0] – Reserved [4] – Error when IO completion entry of NVM#1 is not received until timeout. [5] – Error when status register in IO completion entry of NVM#1 is not 0 or phase tag is invalid. Please see more details from U1IOCompStatus signal. [31:6] – Reserved Note: Timeout period of bit[4] is set from TimeOutSet input.
Data I/F of dgIF typeS
U0FifoWrCnt[15:0]	In	Write data counter of Receive FIFO#0. Used to check full status. If FIFO data counter signal is less than 16 bits, please fill ‘1’ to upper bit.
U0FifoWrEn	Out	Asserted to ‘1’ to write data to Receive FIFO#0 when running Read command with NVM#0.
U0FifoWrData[127:0]	Out	Write data bus of Receive FIFO#0. Valid when U0FifoWrEn=’1’.
U0FifoRdCnt[15:0]	In	Read data counter of Transmit FIFO#0. Used to check data size stored in FIFO. If FIFO data counter signal is less than 16 bits, please fill ‘0’ to upper bit.
U0FifoEmpty	In	The signal is unused for this IP.
U0FifoRdEn	Out	Asserted to ‘1’ to read data from Transmit FIFO#0 when running Write command with NVM#0.
U0FifoRdData[127:0]	In	Read data returned from Transmit FIFO#0. Valid in the next clock after U0FifoRdEn=’1’.
Signals in User#1 I/F use the same description as User#0 I/F by referring to signal and module of NVM#1. User#1 I/F signals consist of U1FifoWrCnt[15:0], U1FifoWrEn, U1FifoWrData[127:0], U1FifoRdCnt[15:0], U1FifoEmpty, U1FifoRdEn, and U1FifoRdData[127:0].

Signal	Dir	Description
muNVMe IP Interface
IPVesion[31:0]	Out	IP version number
U0TestPin[47:0], U1TestPin[15:0]	Out	Reserved to be IP Test point.
TimeOutSet[31:0]	In	Timeout value to wait completion from SSD. Time unit is equal to 1/(Clk frequency). When TimeOutSet is set to 0, Timeout function is disabled.
PCIeLinkup	In	Assert to ‘1’ when LTSSM state of PCIe hard IP is in L0 State.
U0AdmCompStatus[15:0]	Out	Status output from Admin Completion Entry [0] – Set to ‘1’ when Phase tag or Command ID in Admin Completion Entry is invalid. [15:1] – Status field value of Admin Completion Entry
U0IOCompStatus[15:0]	Out	Status output from IO Completion Entry [0] – Set to ‘1’ when Phase tag in IO Completion Entry of NVM#0 is invalid. [15:1] – Status field value of IO Completion Entry in NVM#0.
U1IOCompStatus[15:0]	Out	Description is the same as U0IOCompStatus by referring to signal and module of NVM#1.
NVMeCAPReg[31:0]	Out	The parameter value of the NVMe capability register when U0ErrorType[1] is asserted to ‘1’. [15:0] – MQES (Maximum Queue Entries Supported) [19:16] – DSTRD (Doorbell Stride) [20] – NVM command set flag [24:21] – MPSMIN (Memory Page Size Minimum) [31:25] – Undefined
Identify Ram Interface (for User#0)
IdenWrEn	Out	Asserted to ‘1’ for sending data output from Identify command.
IdenWrDWEn[3:0]	Out	Dword (32-bit) enable of IdenWrData. Valid when IdenWrEn=’1’. ‘1’: this dword data is valid, ‘0’: this dword data is not available. Bit[0], [1], [2], and [3] corresponds to IdenWrData[31:0], [63:32], [95:64], and [127:96] respectively.
IdenWrAddr[8:0]	Out	Index of IdenWrData in 128-bit unit. Valid when IdenWrEn=’1’. 0x000-0x0FF is 4Kbyte Identify controller data, 0x100-0x1FF is 4Kbyte Identify namespace data.
IdenWrData[127:0]	Out	4Kbyte Identify controller data or Identify namespace data. Valid when IdenWrEn=’1’.
Custom Ram Interface (for User#0)
CtmSubmDW0[31:0] – CtmSubmDW15[31:0]	In	16 Dwords of Submission queue entry for SMART/Flush command. DW0: Command Dword0, DW1: Command Dword1, …, and DW15: Command Dword15. These inputs must be valid and stable during U0Req=’1’ and U0Cmd=”100” (SMART) or “110” (Flush).
CtmCompDW0[31:0] – CtmCompDW3[31:0]	Out	4 Dwords of Completion queue entry, output from SMART/Flush command. DW0: Completion Dword0, DW1: Completion Dword1, …, and DW3: Completion Dword3
CtmRamWrEn	Out	Asserted to ‘1’ for sending data output from custom command such as SMART command.
CtmRamWrDWEn[3:0]	Out	Dword (32-bit) enable of CtmRamWrData. Valid when CtmRamWrEn=’1’. ‘1’: this dword data is valid, ‘0’: this dword data is not available. Bit[0], [1], [2], and [3] corresponds to CtmRamWrData[31:0], [63:32], [95:64], and [127:96], respectively.
CtmRamAddr[8:0]	Out	Index of CtmRamWrData when SMART data is received. Valid when CtmRamWrEn=’1’. (Optional) Index to request data input through CtmRamRdData for customized custom commands.
CtmRamWrData[127:0]	Out	512-byte data output from SMART command. Valid when CtmRamWrEn=’1’.
CtmRamRdData[127:0]	In	(Optional) Data input for customized custom commands.

Table 3: Physical I/O Signals for PCIe Gen3 Hard IP (Synchronous to PCIeClk)

Signal	Dir	Description
PCIe Gen3 hard IP
PCIeRstB	In	Synchronous reset signal. Active low. De-assert to ‘1’ when PCIe hard IP is not in reset state.
PCIeClk	In	Clock output from PCIe hard IP (250 MHz for PCIe Gen3).
Configuration Management Interface
PCIeCfgDone	In	Read/Write operation complete. Asserted for 1 cycle when operation completes.
PCIeCfgRdEn	Out	Read enable. Asserted to ‘1’ for a read operation.
PCIeCfgWrEn	Out	Write enable. Asserted to ‘1’ for a write operation.
PCIeCfgWrData[31:0]	Out	Write data which is used to configure the Configuration and Management registers.
PCIeCfgByteEn[3:0]	Out	Byte enable for write data, where bit[0] corresponds to PCIeCfgWrData[7:0], and so on.
PCIeCfgAddr[18:0]	Out	Read/Write Address.
Requester Request Interface
PCIeMtTxData[127:0]	Out	Requester request data bus.
PCIeMtTxKeep[3:0]	Out	Bit [i] indicates that Dword [i] of PCIeMtTxData contains valid data.
PCIeMtTxLast	Out	Asserted this signal in the last cycle of a TLP to indicate the end of the packet.
PCIeMtTxReady[3:0]	In	Assert to accept data. Data is transferred when both PCIeMtTxValid and PCIeMtTxReady are asserted in the same cycle.
PCIeMtTxUser[59:0]	Out	Requester request user data. Valid when PCIeMtTxValid is high.
PCIeMtTxValid	Out	Asserted to drive valid data on PCIeMtTxData bus. muNVMe IP keeps the valid signal asserted during the transfer of a packet.
Completer Request Interface
PCIeMtRxData[127:0]	In	Receive data from PCIe hard IP.
PCIeMtRxKeep[3:0]	In	Bit [i] indicates that Dword [i] of PCIeMtRxData contains valid data.
PCIeMtRxLast	In	Assert this signal in the last beat of a packet to indicate the end of the packet.
PCIeMtRxReady	Out	Indicate that muNVMe IP is ready to accept data.
PCIeMtRxUser[74:0]	In	Sideband information for the TLP being transferred. Valid when PCIeMtRxValid is high.
PCIeMtRxValid	In	Assert when PCIe hard IP drives valid data on PCIeMtRxData bus. PCIe hard IP keeps the valid signal asserted during the transfer of packet.
Completer Completion Interface
PCIeSlTxData[127:0]	Out	Completion data from muNVMe IP.
PCIeSlTxKeep[3:0]	Out	Bit [i] indicates that Dword [i] of PCIeSlTxData contains valid data.
PCIeSlTxLast	Out	Asserted in the last cycle of a packet to indicate the end of the packet.
PCIeSlTxReady[3:0]	In	Indicate that PCIe hard IP is ready to accept data.
PCIeSlTxUser[32:0]	Out	Sideband information for the TLP being transferred. Valid when PCIeSlTxValid is high.
PCIeSlTxValid	Out	Asserted to drive valid data on PCIeSlTxData bus. muNVMe IP keeps the valid signal asserted during the transfer of a packet.
Requester Completion Interface
PCIeSlRxData[127:0]	In	Receive data from PCIe hard IP.
PCIeSlRxKeep[3:0]	In	Bit [i] indicates that Dword [i] of PCIeSlRxData contains valid data.
PCIeSlRxLast	In	Assert this signal in the last beat of a packet to indicate the end of the packet.
PCIeSlRxReady	Out	Indicate that muNVMe IP is ready to accept data.
PCIeSlRxUser[84:0]	In	Sideband information for the TLP being transferred. Valid when PCIeSlRxValid is high.

Timing Diagram

Initialization

Figure 6: Timing diagram during initialization process

The step of the initialization process is as follows.

1) Wait until Clk is stable and then de-assert RstB to ‘1’ to start IP initialization.

2) PCIe hard IP de-asserts PCIeRstB to ‘1’ after PCIe reset sequence is done. PCIe hard IP is ready to transfer data with the application layer.

3) Assert PCIeLinkup to ‘1’ after LTSSM state of PCIe hard IP is L0 state. Though LTSSM state is run on PCIeClk, PCIeLinkup must be generated on Clk domain. Asynchronous register must be applied. After that, muNVMe IP starts initialization process.

4) U0Busy and U1Busy are de-asserted to ‘0’ after muNVMe IP completes initialization process.

After finishing above sequences, muNVMe IP is ready to receive command from user.

Control interface of dgIF typeS

dgIF typeS signals are split into two groups. First group is Control interface for sending command with the parameters and monitoring the status. Second group is Data interface for transferring data stream in both directions. Figure 7 shows dgIF typeS Control interface of NVM#0.

Figure 7: NVM#0 Control Interface of dgIF typeS timing diagram

1) Before sending new command to the IP through User#0 I/F, U0Busy must be equal to ‘0’ to confirm that the desired NVM is the Idle state.

2) Command and the parameters such as U0Cmd, U0Addr, and U0Len must be valid when asserting U0Req to ’1’ for sending the new command request.

3) IP asserts U0Busy to ‘1’ after starting the new command operation.

4) After U0Busy is asserted to ‘1’, U0Req is de-asserted to ‘0’ to finish the current request. New parameters for the next command could be prepared on the bus. U0Req for the new command must not be asserted to ‘1’ until the current command operation is done.

5) U0Busy is de-asserted to ‘0’ after the command operation is completed. New command request could be sent by asserting U0Req to ‘1’.

Note: The number of parameters using in each command is different.

Write and Read command: Use U0Cmd, U0Addr, and U0Len.
SMART and Flush command: Use U0Cmd and CtmSubmDW0-DW15.
Identify and Shutdown command: Use only U0Cmd.

Similarly, dgIF typeS Control interface of NVM#1 has the same concept as NVM#0 by using U1Busy, U1Cmd, U1Addr, and U1Len for Write and Read command.

Figure 8: dgIF typeS Control Interface timing diagram when running command parallelly

Figure 8 shows dgIF TypeS Control interfaces of two user interfaces when NVM#0 and NVM#1 operate the command parallelly. Each user interface has particular control signals to operate user command. Thus, up to two user commands can be operating at the same time, one command through User#0 I/F and another through User#1 I/F. However, Shutdown command is an exemption for this parallel mode.

Data interface of dgIF typeS

Data interface of dgIF typeS is applied for transferring data stream when operating Write command or Read command. The interface is compatible to general FIFO interface. Figure 9 shows dgIF typeS data interface between Transmit FIFO (of UserLogic module) and Data Buffer (of muNVMe IP) when running Write command through User#0 I/F. 16-bit FIFO read data counter (U0FifoRdCnt) shows total amount of data stored in the transmit FIFO before transferring as a burst. The burst size is 512 bytes or 32 cycles of 128-bit data.

Figure 9: Transmit FIFO Interface for NVM#0 Write command

In NVM#0 Write command, data is read from Transmit FIFO#0 until total data are transferred completely. The details to transfer data are described as follows.

1) Before starting a new burst transfer, U0FifoRdCnt[15:5] is monitored. The IP waits until at least 512-byte data is available in Transmit FIFO#0 (U0FifoRdCnt[15:5] is not equal to 0).

2) The IP asserts U0FifoRdEn to ‘1’ for 32 clock cycles to read 512-byte data from Transmit FIFO#0.

3) U0FifoRdData is valid in the next clock cycle after asserting U0FifoRdEn to ‘1’. 32 data are continuously transferred.

4) U0FifoRdEn is de-asserted to ‘0’ after reading the 32^th data (D31). Repeat step 1) – 4) to transfer the next 512-byte data until total amount of data is equal to the transfer size in the command.

5) After total data is completely transferred, U0Busy is de-asserted to ‘0’.

Figure 10: Receive FIFO Interface for User#0 Read command

In NVM#0 Read command, data is transferred from SSD to Receive FIFO#0 of UserLogic until total data are completely transferred. The details to transfer data are as follows.

1) Before starting the new burst transmission, U0FifoWrCnt[15:6] is monitored. The IP waits until the free space of Receive FIFO#0 is enough (U0FifoWrCnt[15:6] is not equal to all 1 or 1023). After received data from the SSD is more than or equal to 512 bytes, the new burst transmission begins.

2) The IP asserts U0FifoWrEn to ‘1’ for 32 clock cycles to transfer 512-byte data from the Data Buffer#0 to UserLogic modue.

3) After finishing transferring 512-byte data, U0FifoWrEn is de-asserted to ‘0’. Repeat step 1) – 3) to transfer the next 512-byte data until total data size is equal to the transfer size in the command.

4) After total data is completely transferred, U0Busy is de-asserted to ‘0’.

Similar to Figure 9 and Figure 10 that show User#0 I/F, dgIF TypeS Data interface of NVM#1 has the same concept by using Transmit FIFO#1, Receive FIFO#1, and Data Buffer#1 to transfer data in NVM#1 Write command and Read command.

As shown in Figure 8 that the command on User#0 I/F and User#1 I/F are requested parallelly. When parallel command is sent, the parallel data on two user interfaces may be found.

Figure 11: dgIF typeS Data Interface timing diagram in parallelly

Figure 11 shows dgIF typeS Data interface of two user interfaces when NVM#0 and NVM#1 receive Write data at the same time. Similarly, the parallel data interface may be found when NVM#0 and NVM#1 operate Read/Read command or Write/Read command.

IdenCtrl/IdenName

It is recommended to send Identify command to the IP as the first command after system boots up. This command updates the necessary information of SSD, i.e., total capacity (LBASize) and LBA unit size (LBAMode). The SSD information is applied to be the limitation of the input parameters when operating Write or Read command, described as follows.

1) The sum of the address (U0Addr and U1Addr) and transfer length (U0Len and U1Len) of Write and Read command must not be more than total capacity (LBASize) of the SSD.

2) If LBAMode of the active SSD is equal to ‘1’ (LBA unit size is 4 Kbytes), the three lower bits (bit[2:0]) of U0Addr, User1Addr, U0Len, and U1Len must be always equal to ‘0’ to align 4-Kbyte unit.

Figure 12: Identify command timing diagram

The details when running Identify command are shown as follows.

1) Send Identify command to the IP through user interface#0 (U0Cmd=000b and U0Req=’1’).

2) The IP asserts U0Busy to ‘1’ after running Identify command.

3) 4096-byte Identify controller data is returned to user. IdenWrAddr is equal to 0-255 with asserting IdenWrEn. Also, IdenWrData and IdenWrDWEn are valid at the same clock as IdenWrEn=’1’.

4) 4096-byte Identify namespace data is returned. IdenWrAddr is equal to 256-511. IdenWrAddr[8] can be applied to check data type which is Identify controller data or Identify namespace data.

5) U0Busy is de-asserted to ‘0’ after the Identify command is done.

6) LBASize and LBAMode of the SSD are simultaneously updated.

Figure 13: IdenWrDWEn timing diagram

IdenWrDWEn is 4-bit signal to be valid signal of 32-bit data. Some SSDs do not return 4-Kbyte Identify controller data and Identify namespace data continuously, but it returns only one dword (32-bit) at a time. Therefore, one bit of IdenWrDWEn is asserted to ‘1’ in the write cycle to write 32-bit data, as shown in Figure 13. IdenWrDWEn[0], [1], [2], and [3] corresponds to IdenWrData[31:0], [63:32], [95:64], and [127:96], respectively.

Shutdown

Shutdown command is recommended to send as the last command before the system is powered down. When Shutdown command is issued, SSD flushes the data from the internal cache to flash memory. After the command is issued, muNVMe IP and SSD are not available until the system is powered down. If the SSD is powered down without Shutdown command, the total count of unsafe shutdowns, read by SMART command, is increased.

Figure 14: Shutdown command timing diagram

The details when running Shutdown command are shown as follows.

1) Before sending the command request, the IP must be in the Idle state (both U0Busy=’0’ and U1Busy=’0’). To send Shutdown command, user asserts U0Req to ‘1’ with U0Cmd=001b.

2) U0Busy is asserted to ‘1’ after muNVMe IP runs Shutdown command.

3) U0Req is de-asserted to ‘0’ to clear the current request when U0Busy is asserted to ‘1’.

4) U0Busy is de-asserted to ‘0’ when the SSD is completely shut down. After that, the IP does not receive any command requested from user.

SMART

SMART command is the command to check the SSD health. After sending SMART command through User#0 I/F, 512-byte health information is returned from the SSD. SMART command loads the parameters from CtmSubmDW0-DW15 signals on Custom command interface. User sets 16-dword data as constant value for SMART command. After that, the SMART data is returned via CtmRAM port as shown in Figure 15.

Figure 15: SMART command timing diagram

The details when running SMART command are shown as follows.

1) Before sending the command request, NVM#0 must be in the Idle state (U0Busy=’0’).

All input parameters must be stable when U0Req is asserted to ‘1’ for sending the request.

CtmSubmDW0-DW15 is set as constant value by following value for SMART command.

CtmSubmDW0 = 0x0000_0002

CtmSubmDW1 = 0xFFFF_FFFF

CtmSubmDW2 – CtmSubmDW5 = 0x0000_0000

CtmSubmDW6 = 0x2000_0000

CtmSubmDW7 – CtmSubmDW9 = 0x0000_0000

CtmSubmDW10 = 0x007F_0002

CtmSubmDW11 – CtmSubmDW15 = 0x0000_0000

2) Assert U0Busy to ‘1’ after muNVMe IP runs SMART command.

3) U0Req is de-asserted to ‘0’ to clear the current request. Next, UserLogic module can change the input parameters for the next command request.

4) 512-byte SMART data is returned on CtmRamWrData signal with asserting CtmRamWrEn to ‘1’. CtmRamAddr is equal to 0-31 to be data index of 512-byte data. When CtmRamAddr=0, byte0-15 of SMART data is valid on CtmRamWrData. CtmRamWrDWEn is dword enable for each 32-bit CtmRamWrData. If CtmRamWrDWEn=1111b, all 128-bit CtmRamWrData are valid.

5) U0Busy is de-asserted to ‘0’ when SMART command is done.

Figure 16: CtmRamWrDWEn timing diagram

Similar to Identify command, some SSDs do not return 512-byte data continuously but returns only one dword (32-bit) at a time. Therefore, one bit of CtmRamWrDWEn is asserted to ‘1’ in the write cycle to be the valid signal of 32-bit CtmRamWrData. CtmRamWrDWEn[0], [1], [2], and [3] corresponds to CtmRamWrData[31:0], [63:32], [95:64], and [127:96], respectively.

Flush

Most SSDs accelerate write performance by storing write data to cache before flushing to the flash memory by the SSD controller. If power is down unexpectedly, the data in the cache may be lost and not stored to the flash memory. Flush command is the command to force the SSD controller to flush data from the cache. After sending Flush command, all data in previous Write command can be guaranteed.

Figure 17: Flush command timing diagram

The details for running Flush command are shown as follows.

1) Before sending the command request, NVM#0 must be in the Idle state (U0Busy=’0’).

All input parameters must be stable when U0Req is asserted to ‘1’ for sending the request.

CtmSubmDW0-DW15 is set as constant value by following value for Flush command.

CtmSubmDW0 = 0x0000_0000

CtmSubmDW1 = 0x0000_0001

CtmSubmDW2 – CtmSubmDW15 = 0x0000_0000

2) U0Busy is asserted to ‘1’ after muNVMe IP runs Flush command.

3) U0Req is de-asserted to ‘0’ to clear the current request. Next, UserLogic module can change the input parameters for the next command request.

4) U0Busy is de-asserted to ‘0’ when Flush command is done.

Error

Figure 18: Error flag timing diagram

If the error is found while running initialization process or operating some commands, U0Error or U1Error flag is asserted to ‘1’, depending on the error interface. ErrorType signal is read to check the occurred error type. For User#0 I/F, NVMeCAPReg, AdmCompStatus, and U0IOCompStatus are valid for monitoring error details after U0Error is asserted to ‘1’. Similarly, U1IOCompStatus is valid for monitoring error details on user interface#1 after U1Error is asserted to ‘1’.

When the error is found while running initialization process, it is recommended to read NVMeCAPReg to check capability of NVMe SSD. When the error is found while operating the command, it is recommended to read AdmCompStatus or U0-U1IOCompStatus, depending on the command type, which is decoded from the received packet.

U0Error and U1Error flag are cleared by RstB signal only. After the failure is solved, RstB is asserted to ‘0’ to clear the error flags.

Verification Methods

The muNVMe IP Core functionality was verified by simulation and also proved on real board design by using KCU116/ZCU106 evaluation board.

Recommended Design Experience

Experience design engineers with a knowledge of Vivado Tools should easily integrate this IP into their design.

Ordering Information

This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. for pricing and additional information about this product using the contact information on the front page of this datasheet.

Revision History

Revision	Date	Description
1.0	14-Jun-2022	Initial Release