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1 Overview 2 Hardware 2.1 TestGen 2.2 NVMe 2.2.1 NVMe-IP 2.2.2 Versal Adaptive SoC CPM Mode / Integrated Block for PCI Express 2.2.3 Dual port RAM. 2.3 CPU and Peripherals 2.3.1 AsyncAxiReg 2.3.2 UserReg 3 CPU Firmware 3.1 Test firmware (nvmeipg5testc) 3.1.1 Identify Command 3.1.2 Write/Read Command 3.1.3 SMART Command 3.1.4 Flush Command 3.1.5 Secure Erase Command 3.1.6 Shutdown Command 3.2 Function list in Test firmware 4 Example Test Result 5 Revision History Return to Top

NVMe-IP for Gen5 reference design manual