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Features Applications General Description Functional Description NVMe Host Controller Cmd FIFO Command Handler Data Buffer Data Controller PCIe PCIe Controller AsyncCtrl User Logic PCIe Hard IP (R-Tile Avalon-ST Intel FPGA for PCIe) Core I/O Signals Timing Diagram. Initialization Control interface (Single mode) Control interface (Multiple mode) Control interface (Parallel command) Read Data stream interface Write Data stream interface Data stream interface (Parallel data) IdenCtrl/IdenName Shutdown SMART Secure Erase Flush Error Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top

rmNVMe IP Core for Gen5 Data Sheet