Design Gateway Co., Ltd

E-mail: ip-sales@design-gateway.com

URL: design-gateway.com

Features

· Byte oriented implementation compatible with FIPS 202

· Supports SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256 in a single unified core.

· Dynamic algorithm and output length selection at runtime using control interface.

· Achieves over 17.5 Gbps @ 316 MHz.

· 64-bit Input/Output AXI4-Stream interface.

· 1344-bit Parallel Output Interface for single-cycle flat hash reading.

· Customizable output length for SHAKE algorithm.

Table 1 Table Description

General Description

The SHA3 IP Core is a hardware-accelerated cryptographic hashing engine that implements all six algorithms defined in FIPS PUB 202: the four fixed-length secure hash functions (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) and the two extendable-output functions (SHAKE128 and SHAKE256). All algorithms share a single unified datapath while supporting dynamic algorithm and output-length selection at runtime.

The SHA3 IP Core is designed for FPGA implementation and targets high-throughput security applications such as post-quantum cryptography infrastructure.

For reference, see: https://csrc.nist.gov/pubs/fips/202/final

Figure 1 SHA3 Block Diagram

Functional Description

The SHA3 IP core allows users to easily implement various SHA3 hash algorithms. Users interact with the core via control signals to configure the algorithm, input data, and manage the hash output. Table 2 shows interface signals of SHA3-IP.

Table 2 Interface signals

Signal name	Dir	Description
Clk	In	IP core system clock.
RstB	In	IP core system reset. Active low.
version[31:0]	Out	32-bit version number of IP.
AXI4-Stream Input Control
SHA3InReady	Out	Asserted to 1 when the core is ready to accept SHA3InData.
SHA3Cmd[2:0]	In	Selects the SHA3/SHAKE algorithm: “000” = SHA3-224, “001” = SHA3-256, “010” = SHA3-384, “011” = SHA3-512, “100” = SHAKE128, “101” = SHAKE256.
SHA3OutLen[31:0]	In	Output hash length in bytes (only for SHAKE128/SHAKE256).
SHA3InValid	In	Asserted to ‘1’ to indicate SHA3InData is valid.
SHA3InLast	In	Asserted to ‘1’ to indicate the last 64-bit word of the input message.
SHA3InByteEn[7:0]	In	Active-high byte-enable mask for the final 64-bit input word.
SHA3InData[63:0]	In	64-bit input message data word to be processed.
Parallel Output Control
ParallelOutValid	Out	Asserted to ‘1’ to indicate the parallel flat output is valid.
ParallelOut[1343:0]	Out	1344-bit flat output.
AXI4-Stream Output Control
StmOutReady	In	Asserted by downstream receiver when ready to accept streamed hash output.
StmOutValid	Out	Asserted to ‘1’ when StmOutData contains valid streamed hash data.
StmOutLast	Out	Asserted to ‘1’ on the final 64-bit word of the squeezed output stream.
StmOutByteEn[7:0]	Out	Active-high byte enables specifying valid bytes in the word of the stream.
StmOutData[63:0]	Out	64-bit streamed hash data.

Note:

* To hash an empty message, assert SHA3InValid and SHA3InLast to ‘1’, and set SHA3InByteEn to x”00”.

Figure 2 Example Timing Diagram of Data Transmission

· Data control

As shown in Figure 2, before sending any data, the user must specify the desired SHA3 or SHAKE algorithm by setting SHA3Cmd[2:0]. If a SHAKE algorithm is selected (SHA3Cmd[2] = ‘1’), the user must also specify the desired output hash length in bytes using SHA3OutLen[31:0]. These values must be valid on the first clock cycle of the input data stream when SHA3InValid and SHA3InReady are asserted. The selected configuration will be used throughout the entire hash operation.

To initiate data transfer, the user must assert SHA3InValid to ‘1’ along with valid data on SHA3InData[63:0]. Data will be accepted by the SHA3-IP only when SHA3InReady is ‘1’. If SHA3InReady is ‘0’, the user must hold all inputs steady until SHA3InReady returns to ‘1’.

During data transfer, SHA3InByteEn[7:0] must be set to “11111111” (8’hFF) to indicate that all 8 bytes of SHA3InData are valid, except on the final word of the message. To mark the final word, the user must assert SHA3InLast to ‘1’ and set SHA3InByteEn[7:0] to reflect the number of valid bytes in that final word (e.g., active-high byte-enable mask from 8’h00 to 8’hFF).

After SHA3InLast is asserted and accepted (both SHA3InValid and SHA3InReady are ‘1’), SHA3InReady will de-assert to ‘0’ in the next clock cycle, indicating that the SHA3-IP is now performing padding and hash computation and will not accept new input until the operation is complete.

· Hash output

Once hash operation complete, ParallelOutValid is asserted to ‘1’, signaling that the hash result is ready on the dedicated parallel output port ParallelOut[1343:0]. The valid output bits depend on the algorithm selected via SHA3Cmd[2:0], as summarized below. Figure 3 covers all SHA3 variants (SHA3-224, SHA3-256, SHA3-384, and SHA3-512), which share the same output sequence but differ in the number of valid bits; Figure 4 covers the SHAKE variants (SHAKE128 and SHAKE256), where the output length is further determined by SHA3OutLen[31:0].

· If SHA3Cmd = “000”, the result (SHA3-224) is valid on ParallelOut[1343:1120].

· If SHA3Cmd = “001”, the result (SHA3-256) is valid on ParallelOut[1343:1088].

· If SHA3Cmd = “010”, the result (SHA3-384) is valid on ParallelOut[1343:960].

· If SHA3Cmd = “011”, the result (SHA3-512) is valid on ParallelOut[1343:832].

· If SHA3Cmd = “100”, the result (SHAKE128) is valid on ParallelOut[1343:0] up to the dynamic byte length specified in SHA3OutLen.

· If SHA3Cmd = “101”, the result (SHAKE256) is valid on ParallelOut[1343:256] up to the dynamic byte length specified in SHA3OutLen.

SHA3InReady will be reasserted to ‘1’ in the next cycle, indicating that the SHA3-IP is ready to accept new input data.

· Stream Hash output

The SHA3-IP supports streaming of hash output through a 64-bit AXI4-Stream data bus. Once the hash computation is complete, StmOutValid will assert to ‘1’, and StmOutData[63:0] will contain the valid hash result. The stream outputs only the valid hash bytes determined by the selected algorithm — equivalent to the valid slice of ParallelOut[1343:x]. To receive the hash output, the user must assert StmOutReady to ‘1’. If StmOutReady is ‘0’, the hash output will be held, and StmOutData[63:0] will not be updated until StmOutReady is asserted again.

During streaming, StmOutByteEn[7:0] indicates which bytes in the current 64-bit word are valid. When the final word of the hash is valid, StmOutLast will assert to ‘1’ to indicate the end of the output stream, and StmOutByteEn[7:0] will reflect the valid bytes in the final word.

If the user does not intend to use the stream hash output, the user must always set StmOutReady to ‘1’.

Figure 3 Example Timing Diagram of SHA-224 Hash Output

Figure 4 Example Timing Diagram of SHAKE128 Hash Output

Verification Methods

The SHA3 IP Core functionality was verified by simulation and also proved on real board design by using Kria KR260 Board.

Recommended Design Experience

The user must be familiar with HDL design methodology to integrate this IP into a system.

Ordering Information

This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. for pricing and additional information about this product, use the contact information on the front page of this datasheet.

Revision History

Revision	Date (D-M-Y)	Description
1.00	4-Jun-26	Initial release