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1 Introduction
2 Hardware Overview
2.1 AsyncAxiReg
2.2 LAxi2TLS
2.3 TLS10GC-IP
2.4 LAxi2TOE
2.5 TOE10GLL
2.6 LL10GEMAC
2.7 Xilinx Transceiver (PMA for 10GBASE-R)
2.8 PMARstCtrl
3 CPU Firmware
3.1 Set FPGAs IP Address
3.2 Set FPGAs Port Number
3.3 Set FPGAs MAC address
3.4 Show key materials
3.5 Show certificate information
3.6 Download data pattern
3.7 Download data in log folder
3.8 Upload data pattern
3.9 Full duplex test
4 Revision History
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TLS10GC-IP Reference Design