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1 Introduction
2 Hardware overview
2.1 100G Ethernet MAC and PHY
2.2 TOE100G-IP
2.3 TXMuxEMAC4to1
2.4 CPU and Peripherals
2.4.1 AsyncAvlReg
2.4.2 UserReg
3 CPU Firmware on FPGA
3.1 Display parameters
3.2 Reset IP
3.3 Half Duplex Test
3.4 Full duplex test
3.5 Function list in User application
4 Test Software on PC
4.1 tcpdatatest for half duplex test
4.2 tcp_client_txrx_single for full duplex test
5 Revision History
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TOE100G-IP 4-Session with CPU reference design