Features Applications General Description Functional Description Control Block Reg TCP Stack Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Async Buffer (Tx) Receive Block Async Buffer (Rx) Packet Filtering Packet Splitter Rx Data Buffer User Block 100G Ethernet MAC and PHY. 12 100G Ethernet MAC and PHY Core I/O Signals Timing Diagram. IP Initialization Register Interface Tx FIFO Interface Rx FIFO Interface EMAC Interface Example usage Client mode (SRV[1:0]=00b) Server mode (SRV[1:0]=01b) Fixed MAC mode (SRV[1] = 1b) PKL and TDL setting in Send command TDL = N times of PKL TDL = N times of PKL + Residue Connection termination of unusual case Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top