TOE10G-IP with CPU Demo Instruction
2.3 Disabling Flow Control and Interrupt Moderation.
3 Test result when using FPGA and PC
4 Test result when using two FPGAs
4.3 Send Data Test (Server to Client)
4.4 Receive Data Test (Client to Server)
1 Overview
This document illustrates an example of running the TOE10G-IP demo using two different test environments to transfer TCP data. The first test environment employs a single FPGA board to transfer TCP data with a PC that runs a test application for transferring TCP data over 10G Ethernet. The performance result may be constrained by the resources of the PC in the specific test environment. On the other hand, the best performance for transferring TCP data using TOE10G-IP can be achieved by utilizing two FPGA boards in the second test environment, where they transfer data to each other.
The document covers three topics, which include setting up the 10G Ethernet connection on the PC to achieve optimal performance for transferring data via 10G Ethernet in section 2. In section 3, the console example and test results are presented when operating under the first test environment, involving FPGA and PC. Lastly, section 4 shows the console example when operating the second test environment, involving FPGA and FPGA. Each topic is described in further detail as follows.
2 PC Setup
This section provides an example of setting up the 10G Network Adapter on a PC to enable Jumbo frames and optimize network performance on Windows 10 OS.
2.1 IP Setting
To set the IP address of the NIC, follow the steps below.
Figure 2‑1 Setting IP address of the NIC on Windows OS
1) Open Local Area Connection Properties of the 10G Ethernet connection, as shown in the left window of Figure 2‑1.
2) Select “TCP/IPv4” and click on Properties.
3) Set the IP address = 192.168.7.25 and the Subnet mask = 255.255.255.0, as shown in the right window of Figure 2‑1.
2.2 Enabling Jumbo Frame
To enable Jumbo Frame of the NIC, follow the steps below.
Figure 2‑2 Jumbo frame setting
1) In the Local Area Connection Properties window, click on “Configure”, as shown in the left windows of Figure 2‑2.
2) In the Advanced Tab, select “Jumbo Packet”. Set the value to “9014 Bytes” to enable Jumbo Frame support, as shown in the right windows of Figure 2‑2.
Note: Setting “Disabled” to disabling Jumbo frame may reduce the performance, so it is advisable to enable it.
2.3 Disabling Flow Control and Interrupt Moderation
To disable the flow control and interrupt moderation of the NIC, follow the steps below.
Figure 2‑3 Disable Flow Control and Interrupt Moderation
1) Select “Flow Control” and set the value to “Disabled”, as shown in the left window of Figure 2‑3.
2) Select “Interrupt Moderation” and set the value to “Disabled”, as shown in the right window of Figure 2‑3.
3) Click the ‘OK’ button to save and exit all the setting windows.
2.4 Power Options Setting
Figure 2‑4 Power options
1) Open the Control Panel and select Power Options, as shown in the left window of Figure 2‑4.
2) Change the setting to High Performance, as shown in the right window of Figure 2‑4.
3 Test result when using FPGA and PC
3.1 Display TCPIP parameters
Choose option ‘0’ to display the TCP/IP parameters. The console will show either eight parameters in Client/Server mode or nine parameters in Fixed-MAC mode.
Figure 3‑1 Display current parameter result
Here are the details of the parameters
1) Window Update Gap: This sets the threshold value for transmitting a Window update packet. The valid value range is 0x00 – 0x3F (0-63), with the threshold value unit being 1 KB. The default value is 16.
2) Reverse Packet: This flag enables the IP to send the retransmitted packet if the IP waits too long for the Window update packet from the target. The default value is ENABLE.
3) Mode: This parameter sets the mode of the TOE10G-IP to initialize in Server, Client, or Fixed-MAC. To initialize the IP in Client mode for operation with the PC, input ‘0’.
4) FPGA MAC address: This parameter sets the 48-bit hex value as the MAC address of the FPGA. The default value is 0x000102030405.
5) FPGA IP: This parameter sets the IP address of FPGA. The default value is 192.168.7.42.
Note: This value is used as Server IP address parameter for the test application on PC.
6) FPGA Port Number: This parameter sets the port number of the FPGA. The default value is 60000.
Note: This value is used as Server port parameter for the test application on PC.
7) Target MAC address (displayed when running Fixed-MAC mode only): This parameter sets the 48-bit hex value as the MAC address of the target device (10G Ethernet on PC). The default value is 0x554433221100.
8) Target IP: This parameter sets the IP address of the target device. The default value is 192.168.7.25.
9) Target Port Number: This parameter sets the port number of the target device to transfer TCP payload data. The default value is 60001.
To change any of these parameters, the user can set them using the menu option [1] (Reset TCPIP parameters).
3.2 Reset TCPIP parameters
Choose option ‘1’ from the menu to reset the IP and modify IP parameters. This menu allows the user to change the IP settings or reset the TOE10G-IP. Upon selection of this option, the current parameters are displayed on the console. Press ‘x’ to keep the same parameters, or press any other key to modify them. Once the parameters are confirmed, the TOE10G-IP is reset and the initialization process begins.
This menu contains eight or nine parameters that must be set. Each parameter is validated before being loaded into the TOE10G-IP. If the input is invalid, the parameter remains unchanged. Once all parameters have been loaded, the IP is reset. The details of each parameter are described in section 3.1(Display TCPIP parameter), and their valid ranges are provided below.
1) Mode: Input ‘0’ to initialize the IP as Client mode.
Note: When the PC and FPGA are connected to different networks, which cannot communicate via the ARP process, the TOE10G-IP must be run in Fixed-MAC mode to manually set the MAC address via the console.
2) Reverse Packet: Set ‘0’ to disable or ‘1’ to enable this feature.
3) Window Update Gap: Set threshold value to transmit Window update packet. The valid range is 0x00 – 0x3F (0-63), with the unit size of the threshold value being 1KB. The default value is 16.
4) FPGA MAC address: Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
5) FPGA IP address: Input four decimal digits separated by “.”, where the valid range for each digit is 0-255.
6) FPGA port number: The valid range is 0-65535.
7) Target MAC address (displayed only when running Fixed-MAC mode): Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
8) Target IP address: Similar to FPGA IP address, this value is a set of four decimal digits.
9) Target port number: The valid range is 0-65535.
After setting the parameters, the final values are displayed on the console. Then, the reset signal is sent to the IP, and it initializes using the new parameters. Finally, “IP initialization complete” is displayed on the console once the initialization process is completed, as shown in Figure 3‑2.
Figure 3‑2 Change IP parameter result
3.3 Send Data Test
Choose option ‘2’ from the menu to send data from the FPGA to the PC. The test application, “tcpdatatest.exe”, is executed on the PC with specified parameters via Command prompt for receiving data. Simultaneously, the user inputs the test parameters for sending data on the FPGA console. The steps to run the test are outlined below.
1) On the FPGA console, input three parameters to initiate the Send data test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
Note: If packet size exceeds 1456 bytes, the packet output from TOE10G-IP will be a jumbo frame. In this case, the PC must support jumbo frames.
c) Mode: This parameter sets the connection mode for the FPGA. Input ‘1’ to open connection in Server mode (Passive open).
3) On the Command prompt, input the test parameters following the recommended values. The “tcpdatatest” application requires six parameters.
>> tcpdatatest <mode> <dir> <server IP> <server port> <bytelen> <pattern>
a) Mode: Input ‘c’ to run the PC as a Client.
b) Dir: Input ‘r’ to run the PC for receiving and verifying test data from the FPGA.
c) Server IP: Input the IP address of the FPGA.
d) Server port: Input the port number of the FPGA.
e) Bytelen: Input the same value as the “Transfer size” from step 1a).
f) Pattern: Input ‘1’ to enable data verification from the FPGA or ‘0’ to skip verification.
4) After running the test application on the PC, the port is created and the current amount of transferred data is displayed on both the FPGA console (transmitted data) and the Command prompt (received data) every second. Once the FPGA completes the transfer, it will close the connection, and the message “Send data complete” will be displayed on the console.
5) Finally, the total transfer size and performance are displayed on the console (transmit performance) and Command prompt (receive performance).
Figure 3‑3 shows an example of the Send data test with basic settings, involving the transmission of packets with non-jumbo frame size and enabling data verification on the test application. The left window displays the FPGA console operating as Server, while the right window displays the Command prompt on the PC operating as Client.
To improve test performance, a maximum packet size requiring Jumbo frame support can be used, as shown in Figure 3‑4.
Figure 3‑3 Send data test by using non-jumbo frame
Figure 3‑4 Send data test by using jumbo frame
If the input is invalid, an error message: “Out-of-range input” or “Invalid input” will be displayed. After that, the operation is cancelled, as shown in Figure 3‑5 - Figure 3‑7.
Figure 3‑5 Error from invalid transfer size
Figure 3‑6 Error from invalid packet size
Figure 3‑7 Error from invalid mode
3.4 Receive Data Test
Choose option ‘3’ from the menu to receive data sent from the PC to the FPGA. The test application, “tcpdatatest.exe”, is executed on the PC with specified parameters via the Command prompt for sending data. Simultaneously, the user inputs the test parameters for receiving and verifying data on the FPGA console. The steps to run the test are outlined below.
1) On the FPGA console, input three parameters to initiate the Receive data test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the PC.
c) Mode: This is the connection mode of the FPGA. Input ‘1’ to open connection in Server mode (Passive open).
2) If all inputs are valid, the recommended parameters to run the test application on the PC will be displayed. The FPGA console will then display “Wait Open connection …”, indicating it is waiting for the application to be run on the PC.
3) On the Command prompt, input the test parameters following the recommended values. The “tcpdatatest” application requires six parameters.
>> tcpdatatest <mode> <dir> <server IP> <server port> <bytelen> <pattern>
a) Mode: Input ‘c’ to run the PC as a Client.
b) Dir: Input ‘t’ to run the PC for sending test data to the FPGA.
c) Server IP: Input the IP address of the FPGA.
d) Server port: Input the port number of the FPGA.
e) Bytelen: Input the same value as the “Transfer size” from step 1a).
f) Pattern: Input the same value as the “Data verification mode” from step 1b). Select ‘0’ to send dummy data or ‘1’ to send incremental data.
4) After running the test application on the PC, the port is created, and the current amount of transferred data is displayed on both the FPGA console (received data) and the Command prompt (transmitted data) every second.
5) Once the PC completes the transfer, it will close the connection. The FPGA console will display “Connection closed” and “Received data completed”. Finally, the total transfer size and performance are displayed on the FPGA console (receive performance) and the Command prompt (transmit performance).
Figure 3‑8 shows an example of the Receive data test with the basic settings of the “tcpdatatest” application on a PC. The application activates incremental data generation. The left window displays the FPGA console (Client), while the right window displays the Command prompt on the PC (Server).
Figure 3‑8 Receive data test with normal settings
To achieve maximum performance in the Receive data test for the specific test environment, the incremental data generation is turned off, and dummy data is transmitted, resulting in the best-case scenario for the test application settings, as shown in Figure 3‑9.
Figure 3‑9 Receive data test with the setting of disabling data verification
Figure 3‑10 provides an error example resulting from data verification failure. The error is caused by a mismatch between the verification mode values of the FPGA and the PC. The FPGA enables data verification, while the “tcpdatatest” application is configured to send dummy data. The error message is displayed on the FPGA console.
Figure 3‑10 Receive data test of data verification failure
3.5 Full Duplex Test
Choose option ‘4’ from the menu to perform a full duplex test on the FPGA and PC, allowing data transfer in both directions simultaneously. The user inputs test parameters on the FPGA console and the PC Command prompt. The “tcp_client_txrx_xg” application is executed on the PC to send and receive data using the same port number. The sequence to run the test is outlined below.
1) On the FPGA console, input four parameters to initiate the full duplex test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
Note: If packet size exceeds 1456 bytes, the packet output from TOE10G-IP will be a jumbo frame. In this case, the PC must support jumbo frame.
c) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the PC.
d) Mode: This parameter sets the connection mode for the FPGA. Input ‘1’ to open connection in Server mode (Passive open).
2) If all inputs are valid, the recommended parameters to run the test application on the PC will be displayed. The FPGA console will then display “Wait Open connection …”, indicating it is waiting for the application to be run on the PC.
3) On the Command prompt, input the test parameters following the recommended values. The “tcp_client_txrx_xg” application requires four parameters.
>> tcp_client_txrx_xg <server IP> <server port> <bytelen> <pattern>
a) Server IP: Input the IP address of the FPGA.
b) Server port: Input the port number of the FPGA.
c) ByteLen: Input the same value as the “Transfer size” from step 1a).
d) Pattern: Input the same value as “Data verification mode” from step 1c).
- ‘0’ to send dummy data and do nothing with the received data.
- ‘1’ to send incremental data and verify the received data.
4) After running the test application on the PC, the port is created, and the current amount of transferred data is displayed on both FPGA console and Command prompt every second.
5) Once the PC (the Client) completes the transfer in both directions, it will close the connection. Finally, the total transfer size and performance are displayed on the FPGA console and Command prompt.
There are a two-second time gap after step 5) for the user to stop the operation by pressing any key on FPGA console and then entering “Ctrl+C” on Command prompt. Otherwise, the process repeats step 4) – 5) in a continuous loop.
Examples of running full-duplex tests with and without data verification are illustrated in Figure 3‑11 and Figure 3‑12, respectively. In specific test environment, disabling data verification shows better overall performance than enabling it. The FPGA console operates as a Client in the left window, while the Command prompt on the PC functions as a Server in the right window.
Figure 3‑11 Full duplex test with enabling data verification
Figure 3‑12 Full duplex test with disabling data verification
4 Test result when using two FPGAs
4.1 Display TCPIP parameter
Choose option ‘0’ to display the TCP/IP parameters. The console will show either eight parameters in Client/Server mode or nine parameters in Fixed-MAC mode.
Figure 4‑1 Display current parameter result
Here are the details of the parameters.
1) Window Update Gap: This sets the threshold value for transmitting a Window update packet. The valid value range is 0x00 – 0x3F (0-63), with the threshold value unit being 1KB. The default value is 16.
2) Reverse Packet: This flag enables the IP to send the retransmitted packet if the IP waits too long for the Window update packet from the target. The default value is ENABLE.
3) Mode: This parameter sets the mode of the TOE10G-IP to initialize in Server, Client, or Fixed-MAC. Input ‘0’ for Client, ‘1’ for Server, or ‘2’ for Fixed-MAC.
4) FPGA MAC address: This parameter sets the 48-bit hex value as the MAC address of the FPGA. The default value is 0x000102030405 (Client/Fixed-MAC mode) or 0x001122334455 (Server mode).
5) FPGA IP: This parameter sets the IP address of the FPGA. The default value is 192.168.7.42 (Client/Fixed-MAC mode) or 192.168.7.25 (Server mode).
6) FPGA Port Number: This parameter sets the port number of the FPGA. The default value is 60000 (Client/Fixed-MAC mode) or 60001 (Server mode).
7) Target MAC address (displayed when running Fixed-MAC mode only): This parameter sets the 48-bit hex value as the MAC address of the target device (another FPGA). The default value is 0x554433221100.
8) Target IP: This parameter sets the IP address of the target device. The default value is 192.168.7.25 (Client/Fixed-MAC mode) or 192.168.7.42 (Server mode).
9) Target Port Number: This parameter sets the port number of the target device to transfer TCP payload data. The default value is 60001 (Client/Fixed-MAC mode) or 60000 (Server mode).
To change any of these parameters, the user can set them using the menu option [1] (Reset TCPIP parameters).
4.2 Reset TCPIP parameters
Choose option ‘1’ from the menu to reset the IP and modify IP parameters. This menu allows the user to change the IP settings or reset the TOE10G-IP. Upon selection of this option, the current parameters are displayed on the console. Press ‘x’ to keep the same parameters, or press any other key to modify them. Once the parameters are confirmed, the TOE10G-IP is reset and the initialization process begins.
This menu contains eight or nine parameters that must be set. Each parameter is validated before being loaded into the TOE10G-IP. If the input is invalid, the parameter remains unchanged. Once all parameters have been loaded, the IP is reset. The details of each parameter are described in section 4.1 (Display TCPIP parameter), and their valid ranges are provided below.
Note:
1. Ensure that two FPGAs are configured in different initialization modes: Server – Client, Client – Fixed MAC, or Fixed MAC – Fixed MAC.
2. When operating in Server – Client mode, if the parameters on the Server need to be reset, the Client FPGA must also be reset. Additionally, the Server must be reset before the Client to ensure that it waits until the ARP request is sent by the Client.
3. It is essential to match the parameters of both FPGAs as listed below.
a. The Target IP address of Board#1 = The FPGA IP address of Board#2
b. The FPGA IP address of Board#1 = The Target IP address of Board#2
c. The Target port number of Board#1 = The FPGA port number of Board#2
d. The FPGA port number of Board#1 = The Target port number of Board#2
1) Mode: Input ‘0’ (Client), ‘1’ (Server), ‘2’ (Fixed-MAC) to determine FPGA initialization mode.
2) Reverse Packet: Set ‘0’ to disable or ‘1’ to enable this feature.
3) Window Update Gap: Set threshold value to transmit Window update packet. The valid range is 0x00 – 0x3F (0-63), with the unit size of the threshold value being 1KB. The default value is 16.
4) FPGA MAC address: Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
5) FPGA IP address: Input four decimal digits separated by “.”, where the valid range for each digit is 0-255.
6) FPGA port number: The valid range is 0-65535.
7) Target MAC address (displayed only when running Fixed-MAC mode): Input 12 digits of hex value, prefixed by “0x” to input it as a hex value.
8) Target IP address: Similar to FPGA IP address, this value is a set of four decimal digits.
9) Target port number: The valid range is 0-65535.
After setting the parameters, the final values are displayed on the console. Then, the reset signal is sent to the IP, and it initializes using the new parameters. Finally, “IP initialization complete” is displayed on the console once the initialization process is completed, as shown in Figure 4‑2 and Figure 4‑3.
Figure 4‑2 Change IP parameter result for Server and Client mode
Figure 4‑3 Change IP parameter result for Fixed-MAC mode
4.3 Send Data Test (Server to Client)
To transmit data from the Server FPGA to the Client FPGA, choose option ‘2’ to initiate the Send data test on the Server FPGA, and select option ‘3’ to initiate the Receive data test on the Client FPGA. The user sets test parameters on both FPGA consoles. The test sequence is outlined below.
Note: The modes configured in the Send data test, Receive data test, and Full duplex test, for communication between two FPGAs determine how the connection is opened and closed. These modes can be configured as active mode (Client) or passive mode (Server). However, this setting is not related to the initialization mode, which is used to configure the FPGAs as a Client or Server mode. It is important to set the two FPGAs to different connection modes, with one being set as the Client and the other as the Server.
1) On the Server console, input three parameters to initiate the Send data test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
c) Mode: This parameter sets the connection mode. Input ‘1’ to open connection in Server mode (Passive open).
2) If all inputs are valid, the Server console will then display “Wait Open connection …”, indicating it is waiting for the Client FPGA to initiate the connection establishment. If any inputs are invalid, the console will display “Out-of-range input” or “Invalid input”, and the operation will be cancelled, similar to the test with PC (as shown in Figure 3‑5 - Figure 3‑7).
3) On the Client console, input three parameters to initiate the Receive data test.
a) Transfer size: The transfer size is specified in bytes. Input the same value as the “Transfer size” from step 1a).
b) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the Server FPGA.
c) Mode: This parameter sets the connection mode. Input ‘0’ to open connection by Client mode (Active open).
4) Once all inputs are valid, the operation begins. The port is created and the console displays the current transfer size on both consoles every second. After sending all data, “Send data complete” is displayed on the Server console.
5) The Server FPGA then closes the connection, and the total transfer size and performance are displayed on both consoles.
In Figure 4‑4, the Server console is displayed on the left window, while the right window displays the Client console. This example demonstrates the performance of the Send data test using a non-jumbo frame size.
When a jumbo frame size is utilized as the packet size, the performance improves, achieving the maximum performance over 10G Ethernet, as demonstrated in Figure 4‑5.
Figure 4‑4 Send data test by using non-jumbo frame
Figure 4‑5 Send data test by using jumbo frame
4.4 Receive Data Test (Client to Server)
This section describes the steps for transferring data from the Client FPGA to the Server FPGA. The Server FPGA must be initiated by selection option ‘3’ to run Received data test before entering option ‘2’ to initiate the Send data test at the Client FPGA. The test sequence is outlined below.
1) On the Server console, input three parameters to initiate the Receive data test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the Client FPGA.
c) Mode: This parameter sets the connection mode. Input ‘1’ to open connection in Server mode (Passive open).
2) If all inputs are valid, the Server console will then display “Wait Open connection …”, indicating it is waiting for the Client FPGA to initiate the connection establishment.
3) On the Client console, input three parameters to initiate the Send data test.
a) Transfer size: The transfer size is specified in bytes. Input the same value as the “Transfer size” from step 1a).
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
c) Mode: This parameter sets the connection mode. Input ‘0’ to open connection by Client mode (Active open).
4) Once all inputs are valid, the operation begins. The port is created and the console displays the current transfer size on both consoles every second. After sending all data, “Send data complete” is displayed on the Client console.
5) The Client FPGA then closes the connection, and the total transfer size and performance are displayed on both consoles.
The left window in Figure 4‑6 shows the Server console, and the right window displays the Client console. Similar to Figure 4‑5, the performance achieved over 10G Ethernet is also maximum when using Jumbo frame size.
Figure 4‑6 Receive data test with data verification
4.5 Full Duplex Test
Choose option ‘4’ to transfer data simultaneously in both directions and run a full duplex test on both the Server FPGA and the Client FPGA. The user sets test parameters on both FPGA consoles. The following sequence illustrates how to run the test.
1) On the Server console, input four parameters to initiate the full duplex test.
a) Transfer size: The transfer size is specified in bytes. The valid range is 0x8 - 0x7_FFFF_FFF8. The input must be aligned to 8 bytes. If inputting a decimal number, enter the digits. For hexadecimal values, prefix the input with “0x”.
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
c) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the Client FPGA.
d) Mode: This parameter sets the connection mode. Input ‘1’ to open connection by Server mode (Passive open).
2) If all inputs are valid, the Server console will then display “Wait Open connection …”, indicating it is waiting for the Client FPGA to initiate the connection establishment.
3) On the Client console, input four parameters to initiate the full duplex test.
a) Transfer size: The transfer size is specified in bytes. Input the same value as the “Transfer size” from step 1a).
b) Packet size: The packet size is specified in bytes. The valid range is 8 – 8960. The input must be aligned to 8 bytes. Similar to the transfer size, decimal values can be entered directly, while hexadecimal values must be prefixed with “0x”.
c) Data verification mode: Set to ‘0’ to disable data verification or ‘1’ to enable data verification to verify data sent from the Server FPGA.
d) Mode: This parameter sets the connection mode. Input ‘0’ to open connection by Client mode (Active open).
4) Once all inputs are valid, the operation begins. The port is created and both consoles display the current transfer size of both transfer directions every second.
5) After transferring all data in both directions completely, the Client FPGA closes the connection. Finally, both consoles display the total transfer size and performance achieved.
There is a two-second time gap after step 5) for the user to stop the operation by pressing any key on both consoles. Otherwise, the operation repeats step 4) – 5) in a continuous loop.
Figure 4‑7 illustrates a full-duplex test between two FPGAs. The left window shows the Server console, while the right window displays the Client console. With the use of the jumbo frame size as the packet size transferred between the two, the full-duplex test attains its maximum performance.
Figure 4‑7 Full duplex test with data verification
5 Revision History
|
Revision |
Date (D/M/Y) |
Description |
|
2.04 |
2-Sep-24 |
Support Fixed-MAC mode for initialization |
|
2.03 |
10-Oct-23 |
Update the test result using ‘tcp_client_txrx_xg’ application. |
|
2.02 |
15-Mar-22 |
Update reversed packet feature |
|
2.01 |
27-Aug-20 |
Correct Figure3-9 |
|
2.00 |
18-Jun-20 |
Remove hardware setup from the document |
|
1.00 |
19-Mar-18 |
Initial version release |