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1 Introduction 2 Hardware overview 2.1 10GBASE-R PHY 2.2 10G EMAC 2.3 TOE10G-IP 2.4 CPU and Peripherals 2.4.1 AsyncAvlReg 2.4.2 UserReg 3 CPU Firmware on FPGA 3.1 Display parameters 3.2 Reset parameters 3.3 Send data test 3.4 Receive data test 3.5 Full duplex test 3.6 Function list in User application 4 Test Software on PC 4.1 “tcpdatatest” for Half Duplex Test 4.2 “tcp_client_txrx_xg” for Full Duplex Test 5 Revision History Return to Top

TOE10G-IP with CPU reference design