Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) TCP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Rx Packet Buffer Packet Filtering Rx Data Buffer User Block 10G Ethernet MAC. 14 10G Ethernet MAC 10G BASE-R PHY. 14 10G BASE-R PHY Core I/O Signals Timing Diagram. IP Reset IP Initialization Connection Establishment Connection Termination Data transmission Data reception Timeout Interrupt Ethernet MAC Interface PKL and TDL setting in ‘Send data’ command TDL = N times of PKL TDL = N times of PKL + Residue Connection termination of unusual case Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top