Applications General Description Functional Description Control Block Parameter Registers (Param Regs) TCP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Rx Packet Buffer Packet Filtering Rx Data Buffer User Block Ethernet MAC and PHY (10GBASE-R) DG 10GEMAC IP Low Latency Ethernet 10G MAC FPGA IP 10G BASE-R PHY IP Ethernet Hard IP Core I/O Signals Timing Diagram. IP Reset IP Initialization Connection Establishment Connection Termination Data Transmission Data Reception Timeout Interrupt Ethernet MAC Interface PKL and TDL setting in Send command TDL = N times of PKL TDL = N times of PKL + Residue Connection Termination and Unusual Case Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top