Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) TCP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Receive Block Rx Packet Buffer Rx Packet Buffer Rx Data Buffer User Block Ethernet Subsystem (10GBASE-R) DG 10G25GEMAC IP The 10G/25G Ethernet Subsystem. The Versal Multirate Ethernet MAC Subsystem. Core I/O Signals Timing Diagram. IP Reset IP initialization Connection Establishment Connection Termination Data Transmission Data Reception Timeout Interrupt Ethernet MAC Interface PKL and TDL setting in Send command TDL = N times of PKL TDL = N times of PKL + Residue Connection Termination and Unusual Case Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top