1 Introduction 2 Hardware overview 2.1 10GBASE-R PHY 2.2 10G EMAC 2.3 TOE10G-IP 2.4 User2MAC 2.4.1 UserTxMAC 2.4.2 UserRxMAC 2.5 CPU and Peripherals 2.5.1 AsyncAvlReg 2.5.2 UserReg 3 CPU firmware on FPGA 3.1 Firmware sequence 3.2 Function list in User application 3.2.1 Function for Operating High-Speed Connection by TOE10G-IP 3.2.2 Function for Operating Low-Speed Connection by CPU (Ping) 4 Test Software on PC 5 Revision History Return to Top