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1 Introduction
2 Hardware Structure
2.1 AXITOE
2.1.1 TOE1G-IP
2.1.2 AXIIF
2.1.3 TOERegIF
2.2 AXIEMAC
2.2.1 TxEMAC
2.2.2 RxEMAC
2.2.3 RegIF
2.3 AsyncAXIReg
3 CPU Firmware
3.1 Receive Data Test
3.2 Send Data Test
3.3 Ping Command Test
4 Necessary consideration
5 Revision History
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TOE1G-IP Two-Port Demo Reference Design Manual