1 Overview 2 Hardware 2.1 Ethernet PHY 2.2 Triple-Speed Ethernet FPGA IP 2.3 MACRegCtrl 2.4 TOE1G-IP 2.5 CPU and Peripherals 2.5.1 AsyncAvlReg 2.5.2 UserReg 3 CPU Firmware (FPGA) 3.1 Display Parameters 3.2 Reset Parameters 3.3 Send Data Test 3.4 Receive Data Test 3.5 Full Duplex Test 3.6 Function List in CPU Firmware 4 Test Software (PC) 4.1 “tcpdatatest” Application (Half Duplex Test) 4.2 “tcp_client_txrx_xg” Application (Full Duplex Test) 5 Revision History Return to Top