1 Introduction 2 Hardware overview 2.1 Ethernet PHY 2.2 Triple speed Ethernet MAC 2.3 MACRegCtrl 2.4 TOE1G-IP 2.5 CPU and Peripherals 2.5.1 AsyncAvlReg 2.5.2 UserReg 3 CPU Firmware on FPGA 3.1 Display parameters 3.2 Reset parameters 3.3 Send data test 3.4 Receive data test 3.5 Full duplex test 3.6 Function list in User application 4 Test Software on PC 4.1 “tcpdatatest” for half duplex test 4.2 “tcp_client_txrx_xg” for full duplex test 5 Revision History Return to Top