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1 Overview 2 Hardware 2.1 Ethernet PHY 2.2 Ethernet MAC 2.3 TOE1G-IP 2.4 CPU and Peripherals 2.4.1 AsyncAxiReg 2.4.2 UserReg 3 CPU Firmware (FPGA) 3.1 Display Parameters 3.2 Reset Parameters 3.3 Send Data Test 3.4 Receive Data Test 3.5 Full Duplex Test 3.6 Function List in CPU Firmware 4 Test Software (PC) 4.1 “tcpdatatest” Application (Half Duplex Test) 4.2 “tcp_client_txrx_xg” Application (Full Duplex Test) 5 Revision History Return to Top

TOE1G-IP With CPU Reference Design Manual