Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) TCP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder EMacFIFO Receive Block Rx Packet Buffer Packet Filtering Rx Data Buffer User Logic Ethernet MAC Core I/O Signals Timing Diagram. IP Reset IP Initialization Connection Establishment Connection Termination Data Transmission Data Reception Timeout Interrupt Ethernet MAC Interface PKL and TDL setting in ‘Send data’ command TDL = N times of PKL TDL = N times of PKL + Residue Connection Termination of Unusual Case Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top