FPGA Setup for TOE/UDP1G IP with CPU Demo
2 Test Environment Setup Using FPGA and PC
3 Test Environment Setup Using Two FPGAs
1 Overview
This document explains how to setup the FPGA board and prepare the test environment for running the TOE1G-IP or UDP1G-IP demo. Users can setup one of two test environments for transferring TCP data or UDP data over 1Gb Ethernet connection using TOE1G-IP or UDP1G-IP, as illustrated in Figure 1.
Figure 1 Two Test Environments of This Demo
The first setup uses one FPGA board and a PC with a 1Gb Ethernet card for data transfer. The PC runs one of the following test applications: tcpdatatest (half-duplex test for TOE1G-IP), tcp_client_txrx_xg for (full-duplex test for TOE1G-IP), or udpdatatest (test application for UDP1G-IP). Additionally, the PC runs the Serial console as the user interface console.
The second setup involves two FPGA boards, which can be either the same or different boards. Both boards run the TOE1G-IP or UDP1G-IP demo with specific initialization mode assigned (Client, Server, or Fixed-MAC) to facilitate data transfer.
2 Test Environment Setup Using FPGA and PC
Before running the demo with an FPGA and PC, please prepare the following.
Hardware Requirements
· FPGA development boards: AC701, KC705, ZC706, and KCU105 boards.
· PC equipped with a 1 Gigabit Ethernet port or a 1 Gigabit Ethernet card.
· For ZC706 only: An SFP to RJ45 adapter is required.
· 1Gb Ethernet cable: Use a Cat5e or Cat6 cable to connect the FPGA and PC.
· USB cables for FPGA-to-PC connections (for FPGA programming and JTAG UART):
o AC701, KC705, and ZC706: A mini-USB cable for FPGA programming and a micro-USB cable for the Serial console.
o KCU105: Two micro-USB cables (one for FPGA programming and one for the Serial console).
Software Requirements
· Test application provided by Design Gateway for running on the PC:
o TOE1G-IP: Use “tcpdatatest.exe” and “tcp_client_txrx_xg.exe”.
o UDP1G-IP: Use “udpdatatest.exe”.
· Software installed on PC
o Vivado programming tools for FPGA programming.
o Serial console software (e.g., TeraTerm) with the following settings:
§ Baud rate: 115,200
§ Data: 8-bit
§ Parity: None
§ Stop bits: 1-bit
Figure 2 TOE1G-IP/UDP1G-IP with CPU Demo (FPGA<->PC) on ZC706
Figure 3 TOE1G-IP / UDP1G-IP with CPU Demo (FPGA<->PC) on KC705
Figure 4 TOE1G-IP/UDP1G-IP with CPU Demo on AC701
Figure 5 TOE1G-IP/UDP1G-IP with CPU Demo on KCU105
Follow these steps to set up a test environment using an FPGA board and a PC.
1) Turn off the power switch and connect the power supply to the FPGA board.
2) For ZC706 board, check the DIPSW settings on the board:
· Set SW11 = all OFF to configure PS from JTAG.
· Set SW4[1:2] = OFF ON to use USB-JTAG.
Figure 6 DIPSW Settings for ZC706
3) Connect the appropriate USB cables (micro-USB or mini-USB cable depending on FPGA board) to the PC for FPGA programming and USB UART.
4) Use a CAT5e/CAT6 cable to establish an Ethernet connection between the FPGA board and the PC. For ZC706 only, insert an SFP-to-RJ45 adapter into SFP+ connector before connecting the CAT cable.
Figure 7 Ethernet Connection
5) Turn on the power switch on the FPGA board.
6) Open the Serial console software and configure the following settings: Baud rate=115,200; Data=8-bit; Parity=None; Stops bits=1-bit. For KCU105 only, multiple COM ports from the FPGA connection are detected in the PC’s Device Manager. In this case, select the Standard COM port for communication.
Figure 8 COM Port Selection and Serial Console Setting
7) Download configuration file and firmware to the FPGA board.
· For ZC706 board: Open the Vivado TCL shell and change the current directory to the download folder that contains the demo configuration file. Type “<ip>1gcputest_<board>.bat”, as shown in Figure 9.
Figure 9 Download File Command script for Zynq Series Boards using Vivado Tcl Shell
· For other bords: use the Vivado programming to download the configuration file, as shown in Figure 10.
Figure 10 FPGA Configuration using Device Programmer on Vivado
8) Upon opening the Serial console, a welcome message will be displayed. Initialize the IP core following these steps:
i) Enter ‘0’ to initialize the TOE1G-IP/UDP1G-IP in Client mode, ensuring that both the PC and FPGA are on the same network. In this mode, the ARP request packet is generated to retrieve the PC’s MAC address.
ii) The default parameters for the Client mode will be displayed on the console.
Figure 11 Boot-up Message
iii) If the user wishes the skip parameter setting and use default parameters to start the system initialization, input ‘x’ as shown in Figure 12. If any other keys are entered, the menu for changing parameter will appear, similar to the “Reset TCPIP/UDPIP parameters” menu. The example of running the main menu of the IP is described in “dg_toe1gip_cpu_instruction” / “dg_udp1gip_cpu_instruction document.
Figure 12 Initialization Complete
Note: Transfer performance in the demo is limited by the PC performance.
3 Test Environment Setup Using Two FPGAs
Before running the demo with two FPGAs, prepare the following items.
Hardware Requirements
· Two FPGA development boards (these can be the same or different models): AC701, KC705, ZC706, and KCU105 boards.
· For ZC706 only: An SFP to RJ45 adapter is required.
· Use a Cat5e or Cat6 cable for a 1 Gb Ethernet connection between two FPGA boards. The connection can be made directly between the FPGA boards or through network devices such as Ethernet switch.
· USB cables for FPGA-to-PC connections (for FPGA programming and JTAG UART):
o AC701, KC705, and ZC706: A mini-USB cable for FPGA programming and a micro-USB cable for the Serial console.
o KCU105: Two micro-USB cables (one for FPGA programming and one for the Serial console).
Software Requirements
· Software installed on PC
o Vivado programming tools for FPGA programming.
o Serial console software (e.g., TeraTerm) with the following settings:
§ Baud rate: 115,200
§ Data: 8-bit
§ Parity: None
§ Stop bits: 1-bit
Figure 13 TOE1G-IP/UDP1G-IP with CPU Demo (FPGA<->FPGA)
The steps for setting up a test environment using two FPGAs are described below.
To get started with the demo, follow all steps, except the last step, in Section 2 (Test Environment Setup Using FPGA and PC) to prepare each FPGA board and establish the Ethernet connection for the demo. Once you have completed the configuration for two FPGA boards, a menu will be displayed in the console for selecting Client mode, Server mode, or Fixed-MAC mode. Follow the detailed steps below to continue the demo.
1) Open the Serial console for FPGA board#1 and FPGA board#2. Enter the appropriate input to initialize the system in Server, Client, or Fixed-MAC mode. Figure 14 illustrates the initialization process in Server<->Client mode, following these steps.
i) On the FPGA#1 console, enter ‘1’ to run in Server mode.
ii) On the FPGA#2 console, enter ‘0’ to run in Client mode.
iii) The default parameters for the selected mode will be displayed on the console.
Note: The rules for setting the initialization mode are below.
· If two FPGA bords are on the same network, three initialization modes can be used: Server <-> Client, Fixed-MAC <-> Fixed-MAC, and Fixed-MAC <-> Client.
· If two FPGA boards are on different network, both boards must be configured by Fixed-MAC mode.
Figure 14 Default Parameters
2) Input ‘x’ to use default parameters or use other keys to change parameters. The parameters of Server mode must be set before Client mode.
TOE1G-IP
i) Set parameters on the Server console (FPGA#1 console).
ii) Set parameters on Client console (FPGA#2 console) to start IP initialization by transferring ARP packet.
iii) After finishing the initialization process. “IP initialization complete” and the main menu are displayed on both consoles.
Figure 15 TOE1G-IP Main Menu
UDP1G-IP
i) For Server mode, if the default parameters are not changed, input ‘x’ to skip parameter configuration.
ii) For Client mode, ensure the target port number (Target->FPGA) of the Client board matches the target port number (FPGA->Target) of the Server board before proceeding.
iii) Once the initialization process is complete, the message “IP initialization complete” is displayed, followed by the main menu on both consoles.
Figure 16 UDP1G-IP Main Menu
4 Revision History
|
Revision |
Date (D-M-Y) |
Description |
|
3.01 |
11-Mar-25 |
Support Fixed-MAC mode |
|
3.00 |
10-Nov-20 |
Merge TOE1G-IP and UDP1G-IP for shared document |
|
2.00 |
31-Jul-20 |
Remove the result on the console |
|
1.00 |
2-Nov-18 |
Initial version release |