Features Applications General Description Functional Description Control Block Reg UDP Stack Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Async Buffer (Tx) Receive Block Async Buffer (Rx) Packet Filtering Packet Splitter Rx Data Buffer User Block 100G Ethernet IP. 8 100G Ethernet IP Core-I/O Signals Timing Diagram. IP Initialization Register Interface Tx FIFO Interface Rx FIFO Interface EMAC Interface Example usage Client mode (SRV[1:0]=?00?) Server mode (SRV[1:0]=?01?) Fixed MAC mode (SRV[1:0]=?1x?) Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top