Features Applications General Description Functional Description Control Block Parameter Registers (Param Regs) UDP/IP Engine Transmit Block Tx Data Buffer Tx Packet Buffer Packet Builder Async Buffer (Tx) Receive Block Async Buffer (Rx) Packet Filtering Packet Splitter Rx Data Buffer User Block 100G Ethernet (MAC) Subsystem.. 8 100G Ethernet (MAC) Subsystem. AMD 100G Ethernet Subsystem (UltraScale+) AMD 100G Ethernet MAC Subsystem (Versal) Core I/O Signals Timing Diagram. IP Reset IP Initialization Data Transmission Data Reception Interrupt Ethernet MAC Interface Verification Methods Recommended Design Experience Ordering Information Revision History Return to Top